Trying to understand how to solve this. ## Constructing a State Diagram for a Sequence Detector### OverviewThis exercise involves building a state diagram for a finite-state machine (FSM) used as a sequence detector. The FSM processes a 1-bit input \( v \) and produces a 1-bit output \( g \).### Functionality- **Input:** A 4-bit sequence.- **Output:** The FSM sets the output to 0 for the first three bits of each sequence. It outputs 1 on the fourth bit only if the sequence matches one of these binary strings: `0000`, `0011`, or `0111`.- **Type:** This FSM is a Mealy-type machine, meaning the output is determined by both the current state and the current input.- **Reset:** The machine resets to the initial state after processing each 4-bit sequence.- **Non-overlapping Patterns:** The input sequences do not overlap during processing.### Sample BehaviorTo illustrate how this FSM functions, consider the following example. Spaces are inserted between each 4-bit sequence for clarity. Note that this example demonstrates the machine's ability to process and reset after each sequence, ensuring recognition of the specified patterns without overlap. **Finite State Machine Example**This example demonstrates some sample behavior of a finite state machine (FSM). Spaces are added between each 4-bit input sequence for clarity.- **Input Sequence (v):** 1000 0000 0000 0111 0101 0011- **Output Sequence (g):** 0000 0001 0001 0001 0000 0001**Task: FSM State Reduction**Your task is to fully reduce the number of states in your FSM and construct the reduced state table.

A finite state machine (FSM) is a computation model that can be used to simulate sequential logic or to represent and regulate execution flow in other words. Finite state machines can be used to model problems in a variety of domains, including mathematics, AI, gaming, and linguistics. A finite-state machine, also known as a finite automaton or a state machine, is a mathematical model of computation. It's a machine that can be only in one of a finite set of states at a given time. Other models of computation, such as the Turing machine, have more processing capacity than the finite-state machine.FSM will be in the reset state at first.If the input is 1, it will move to the not-useful state sequence from the reset state, and if the input is 0, it will proceed to the helpful state sequence, as the sequences to be detected are 0000, 0011, 0111. Because the FSM must reach the reset state after 4 inputs and fresh sequence detection must begin after 4 inputs, we add a few extra states to ensure that it reaches the reset state only at the end of the fourth input. Detection of whether or not the needed sequence is present:A basic state diagram with state labels with just the input sequence to remember is given below for your convenience. Let's call the states S_RESET, S_0, S_00, and a few more, as well as S_N1, S_N2, and S_N3 to indicate states that aren't relevant. So, there are a total of 10 states.