1. Construct a state diagram for the following sequence detector. The finite-state machine (FSM) has a 1-bit input v and 1-bit output g. For each 4-bit input sequence, the output is 0 for the first three bits.
1. Construct a state diagram for the following sequence detector. The finite-state machine (FSM) has a 1-bit input v and 1-bit output g. For each 4-bit input sequence, the output is 0 for the first three bits.
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1. Construct a state diagram for
the following sequence detector.
The finite-state machine (FSM) has
a 1-bit input v and 1-bit output g.
For each 4-bit input sequence, the
output is 0 for the first three bits,
then 1 on the fourth
if the 4-bit
sequence matches one of the
binary strings 0000, 0011, or 011.
This is a Mealy-type FSM. The
machine returns to the reset state
after each 4-bit sequence. Note
that the input patterns do not
overlap.
Some sample behavior of the finite
state machine is the following.
The example puts a space between
each 4-bit input sequence to make
them easy to see.](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Ff975724c-f6e6-4f11-80b9-86a7fa975ad8%2F1ecbd5d8-a07b-487d-8e6d-3a94f0f413a9%2Farxfyup_processed.jpeg&w=3840&q=75)
Transcribed Image Text:3:21
1 Search
1. Construct a state diagram for
the following sequence detector.
The finite-state machine (FSM) has
a 1-bit input v and 1-bit output g.
For each 4-bit input sequence, the
output is 0 for the first three bits,
then 1 on the fourth
if the 4-bit
sequence matches one of the
binary strings 0000, 0011, or 011.
This is a Mealy-type FSM. The
machine returns to the reset state
after each 4-bit sequence. Note
that the input patterns do not
overlap.
Some sample behavior of the finite
state machine is the following.
The example puts a space between
each 4-bit input sequence to make
them easy to see.
![3:43
Some sample behavior of the finite
state machine is the following.
The example puts a space between
each 4-bit input sequence to make
them easy to see.
v = 1000 0000 0000 0111 0101 0011
g = 0000 0001 0001 0001 0000 0001
2. Fully reduce the number of
states in FSM and construct
your
the reduced state table.](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Ff975724c-f6e6-4f11-80b9-86a7fa975ad8%2F1ecbd5d8-a07b-487d-8e6d-3a94f0f413a9%2Fafsdgz_processed.jpeg&w=3840&q=75)
Transcribed Image Text:3:43
Some sample behavior of the finite
state machine is the following.
The example puts a space between
each 4-bit input sequence to make
them easy to see.
v = 1000 0000 0000 0111 0101 0011
g = 0000 0001 0001 0001 0000 0001
2. Fully reduce the number of
states in FSM and construct
your
the reduced state table.
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