1. Consider the ARM7TDMI data path pictured below: A

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1. Consider the ARM7TDMI data path pictured below:
A (S1:0)
ALE
Scan
Control
Addres Reglster
Address
Incrementer
DBGROI
BREAKPTI
DBGACK
ECLK
NEKEC
Register Bank
ISYNC
BL
APE
MC LK.
EnWAIT
nRW
MAS (1:0)
nIRO
(31x 32-bit reglatera)
I6 status regieters)
Instruction
Decoder
32x4
Multiplier
EnRESET
ABORT
nTRANS
MR EQ
+nOPC
SEO
LOCK
CPI
CPA
CPB
M (401
-TBE
+ TBIT
HIGHZ
Control
Logic
Barel
Shifter
32-bit ALU
Instruction Pipeline
& Read Data Register
& Thumb Instruction Decoder
White Data Regiater
nEN duT Ineh IN
Now, consider the 3 stages of the ARM7TDMI pipeline of fetch, decode,
and execute. Considering a data processing instruction (that does not
touch memory when executing), list which elements of the data path is
controlled by the following pipeline stage:
a. Fetch:
b. Decode:
с. Еxecute:
Transcribed Image Text:1. Consider the ARM7TDMI data path pictured below: A (S1:0) ALE Scan Control Addres Reglster Address Incrementer DBGROI BREAKPTI DBGACK ECLK NEKEC Register Bank ISYNC BL APE MC LK. EnWAIT nRW MAS (1:0) nIRO (31x 32-bit reglatera) I6 status regieters) Instruction Decoder 32x4 Multiplier EnRESET ABORT nTRANS MR EQ +nOPC SEO LOCK CPI CPA CPB M (401 -TBE + TBIT HIGHZ Control Logic Barel Shifter 32-bit ALU Instruction Pipeline & Read Data Register & Thumb Instruction Decoder White Data Regiater nEN duT Ineh IN Now, consider the 3 stages of the ARM7TDMI pipeline of fetch, decode, and execute. Considering a data processing instruction (that does not touch memory when executing), list which elements of the data path is controlled by the following pipeline stage: a. Fetch: b. Decode: с. Еxecute:
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