1. Consider a 2-bit counter with an active-high enable (E) that counts in the following sequence: 00, 01, 11, 10, 00, 01,... There are 4 states, so 2 FFs needed to implement the counter. a. Draw the state diagram for this counter. b. Create a table of the inputs, present states, next states, and the required inputs for a D- FF implementation (inputs: D1 & D0, outputs: Q1 & Q0). The table will be similar to the tables on slides 20 and 14. c. Determine the minimized combinational logic expressions to create the inputs to the D-FFs.
1. Consider a 2-bit counter with an active-high enable (E) that counts in the following sequence: 00, 01, 11, 10, 00, 01,... There are 4 states, so 2 FFs needed to implement the counter. a. Draw the state diagram for this counter. b. Create a table of the inputs, present states, next states, and the required inputs for a D- FF implementation (inputs: D1 & D0, outputs: Q1 & Q0). The table will be similar to the tables on slides 20 and 14. c. Determine the minimized combinational logic expressions to create the inputs to the D-FFs.
Introductory Circuit Analysis (13th Edition)
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ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
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
Transcribed Image Text:1. Consider a 2-bit counter with an active-high enable (E) that counts in the following sequence:
00, 01, 11, 10, 00, 01,... There are 4 states, so 2 FFs needed to implement the counter.
a. Draw the state diagram for this counter.
b.
Create a table of the inputs, present states, next states, and the required inputs for a D-
FF implementation (inputs: D1 & D0, outputs: Q1 & Q0). The table will be similar to
the tables on slides 20 and 14.
c. Determine the minimized combinational logic expressions to create the inputs to the
D-FFs.
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