1. 2-way Set Associative Cache Memory Consider a hypothetical machine with 1K words of cache memory. They are in two-way set associative organization, with cache block size of 128 words, using LRU replacement algorithm. Suppose the cache hit time is 10ns, the time to transfer the first word from main memory to cache is 60ns, while subsequent words require 12ns/word. Consider the following read pattern (in blocks of 128 words, and block id starts from 0): 1 2 3 5 6 2 3 4 9 10 11 6 3 6 1 7 8 4 5 9 11 1 2 4 5 12 13 14 15 13 14 and assume each block contains an average of 48 references. (a) What is the cache miss penalty (i.e., time to transfer one block of data from main memory to cache memory)? (b) Write down the content of the cache memory (for all the blocks) at the end of the memory references, assuming that the cache is empty at the beginning. (c) Write down the number of cache misses (the first reading of a block is also considered a miss), and the cache hit rate. (d) Calculate the average memory access time. 2. Direct-Mapped Cache Memory Redo Question 1 if the cache size is the same, but in direct-mapped organization, and the cache hit time is 9ns instead
1. 2-way Set Associative Cache Memory Consider a hypothetical machine with 1K words of cache memory. They are in two-way set associative organization, with cache block size of 128 words, using LRU replacement algorithm. Suppose the cache hit time is 10ns, the time to transfer the first word from main memory to cache is 60ns, while subsequent words require 12ns/word. Consider the following read pattern (in blocks of 128 words, and block id starts from 0): 1 2 3 5 6 2 3 4 9 10 11 6 3 6 1 7 8 4 5 9 11 1 2 4 5 12 13 14 15 13 14 and assume each block contains an average of 48 references. (a) What is the cache miss penalty (i.e., time to transfer one block of data from main memory to cache memory)? (b) Write down the content of the cache memory (for all the blocks) at the end of the memory references, assuming that the cache is empty at the beginning. (c) Write down the number of cache misses (the first reading of a block is also considered a miss), and the cache hit rate. (d) Calculate the average memory access time. 2. Direct-Mapped Cache Memory Redo Question 1 if the cache size is the same, but in direct-mapped organization, and the cache hit time is 9ns instead
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
Related questions
Question
Please written by computer source
QUESTION 2 ONLY PLEASE!!!
Expert Solution
This question has been solved!
Explore an expertly crafted, step-by-step solution for a thorough understanding of key concepts.
This is a popular solution!
Trending now
This is a popular solution!
Step by step
Solved in 2 steps
Knowledge Booster
Learn more about
Need a deep-dive on the concept behind this application? Look no further. Learn more about this topic, computer-science and related others by exploring similar questions and additional content below.Similar questions
Recommended textbooks for you
Database System Concepts
Computer Science
ISBN:
9780078022159
Author:
Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:
McGraw-Hill Education
Starting Out with Python (4th Edition)
Computer Science
ISBN:
9780134444321
Author:
Tony Gaddis
Publisher:
PEARSON
Digital Fundamentals (11th Edition)
Computer Science
ISBN:
9780132737968
Author:
Thomas L. Floyd
Publisher:
PEARSON
Database System Concepts
Computer Science
ISBN:
9780078022159
Author:
Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:
McGraw-Hill Education
Starting Out with Python (4th Edition)
Computer Science
ISBN:
9780134444321
Author:
Tony Gaddis
Publisher:
PEARSON
Digital Fundamentals (11th Edition)
Computer Science
ISBN:
9780132737968
Author:
Thomas L. Floyd
Publisher:
PEARSON
C How to Program (8th Edition)
Computer Science
ISBN:
9780133976892
Author:
Paul J. Deitel, Harvey Deitel
Publisher:
PEARSON
Database Systems: Design, Implementation, & Manag…
Computer Science
ISBN:
9781337627900
Author:
Carlos Coronel, Steven Morris
Publisher:
Cengage Learning
Programmable Logic Controllers
Computer Science
ISBN:
9780073373843
Author:
Frank D. Petruzella
Publisher:
McGraw-Hill Education