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(1) What's the average latency of a memory access? (2) What's the speedup rate of the access if the L2 cache miss-rate can be reduced to 9%? (3) There are three candidate choices, i.e., direct-mapped, set-associativity, and full-associativity, to construct the L1 cache. Which one could you like to pick for the L1 cache? Please explain the reason of your choice. .

(1) What's the average latency of a memory access? (2) What's the speedup rate of the access if the L2 cache miss-rate can be reduced to 9%? (3) There are three candidate choices, i.e., direct-mapped, set-associativity, and full-associativity, to construct the L1 cache. Which one could you like to pick for the L1 cache? Please explain the reason of your choice. .

Database System Concepts
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
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A commercial single-core CPU includes three levels of cache. The latency from L1 to memory are 3 cycles, 20 cycles, 80 cycles, and 200 cycles. A cache-level trace shows that, under a specific running context, the miss rates of L1, L2, and L3 cache are 15%, 10%, and 5%. (1) What's the average latency of a memory access? (2) What's the speedup rate of the access if the L2 cache miss-rate can be reduced to 9%? (3) There are three candidate choices, i.e., direct-mapped, set-associativity, and full-associativity, to construct the L1 cache. Which one could you like to pick for the L1 cache? Please explain the reason of your choice.
Transcribed Image Text:A commercial single-core CPU includes three levels of cache. The latency from L1 to memory are 3 cycles, 20 cycles, 80 cycles, and 200 cycles. A cache-level trace shows that, under a specific running context, the miss rates of L1, L2, and L3 cache are 15%, 10%, and 5%. (1) What's the average latency of a memory access? (2) What's the speedup rate of the access if the L2 cache miss-rate can be reduced to 9%? (3) There are three candidate choices, i.e., direct-mapped, set-associativity, and full-associativity, to construct the L1 cache. Which one could you like to pick for the L1 cache? Please explain the reason of your choice.
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