Please give me correct solution for all Questions. A commercial single-core CPU includes three levels of cache. The latency from L1 tomemory are 3 cycles, 20 cycles, 80 cycles, and 200 cycles. A cache-level trace showsthat, under a specific running context, the miss rates of L1, L2, and L3 cache are 15%,10%, and 5%.(1) What's the average latency of a memory access?(2) What's the speedup rate of the access if the L2 cache miss-rate can be reducedto 9%?(3) There are three candidate choices, i.e., direct-mapped, set-associativity, andfull-associativity, to construct the L1 cache. Which one could you like to pickfor the L1 cache? Please explain the reason of your choice.

1. Average Latency :=> (0.85 * 3)[if hit inL1] + (0.15) { {3+(0.90*20))[if miss in l1 and hit…

(1) What's the average latency of a memory access? (2) What's the speedup rate of the access if the L2 cache miss-rate can be reduced to 9%? (3) There are three candidate choices, i.e., direct-mapped, set-associativity, and full-associativity, to construct the L1 cache. Which one could you like to pick for the L1 cache? Please explain the reason of your choice. .

(1) What's the average latency of a memory access? (2) What's the speedup rate of the access if the L2 cache miss-rate can be reduced to 9%? (3) There are three candidate choices, i.e., direct-mapped, set-associativity, and full-associativity, to construct the L1 cache. Which one could you like to pick for the L1 cache? Please explain the reason of your choice. .

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 4PE

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