1 12 1 1 13 1 14 1 15 Table (1) Truth table for a 4-stage binary up counter Procedure: 1. Hook up the counter shown in fig. (1-1) on the logic simulator. 2. Give a clock pulse the number 0001 appears. (This appears as "1000" since FF0 contains the least significant bits). 3. Continue to give a clock pulses and observe that the count progresses to "1111" (15) and resets on the 16th pulse. 4. Increase the frequency of the clock pulse, the counter is still counting but at a higher speed. 5. Design a four stage asynchronous "DOWN" counter then prepare its truth table using logic simulator. Discussion: How many flip-flops are needed in an up-asynchronous counter which can count up to 63. 2. Design a three up-down asynchronous counter such that the up or down counter is selected by a switch. Connect and verify operation. 3. Design a mod-7 asynchronous counter. 的 HIGH FFO FFI FF2 FF3 CLK >C K,

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
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Table (1) Truth table for a 4-stage binary up counter
Procedure:
1. Hook up the counter shown in fig. (1-1) on the logic simulator.
2. Give a clock pulse the number 0001 appears. (This appears as "1000" since
FF0 contains the least significant bits).
3. Continue to give a clock pulses and observe that the count progresses to
"1111" (15) and resets on the 16th pulse.
4. Increase the frequency of the clock pulse, the counter is still counting but at a
higher speed.
5. Design a four stage asynchronous "DOWN" counter then prepare its truth
table using logic simulator.
Discussion:
How many flip-flops are needed in an up-asynchronous counter which can
count up to 63.
2. Design a three up-down asynchronous counter such that the up or down counter
is selected by a switch. Connect and verify operation.
3. Design a mod-7 asynchronous counter.
0000
HIGH
FFO
FFI
FF2
FF3
CLK
>C
K,
K
K,
Transcribed Image Text:1 1 12 1 13 1 1 14 15 Table (1) Truth table for a 4-stage binary up counter Procedure: 1. Hook up the counter shown in fig. (1-1) on the logic simulator. 2. Give a clock pulse the number 0001 appears. (This appears as "1000" since FF0 contains the least significant bits). 3. Continue to give a clock pulses and observe that the count progresses to "1111" (15) and resets on the 16th pulse. 4. Increase the frequency of the clock pulse, the counter is still counting but at a higher speed. 5. Design a four stage asynchronous "DOWN" counter then prepare its truth table using logic simulator. Discussion: How many flip-flops are needed in an up-asynchronous counter which can count up to 63. 2. Design a three up-down asynchronous counter such that the up or down counter is selected by a switch. Connect and verify operation. 3. Design a mod-7 asynchronous counter. 0000 HIGH FFO FFI FF2 FF3 CLK >C K, K K,
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