. 19. We pointed out that I/O buses do not need separate address lines. Construct a timing diagram similar to Figure 7.11 that describes the handshake between an I/O controller and a disk controller for a write operation. (Hint: You will need to add a control signal.)

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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TimeSalient Bus SignalMeaning
t₂
ts
Assert
Read
Assert
Address
Assert
Request
Data Lines
Assert
Ready
Lower
Request
Lower
Ready
Bus is needed for reading (not writing)
Indicates where bytes will be written
Request read to address on address lines
Read data (requires several cycles)
Acknowledges read request, bytes placed
on data lines
Request signal no longer needed
Release bus
Transcribed Image Text:TimeSalient Bus SignalMeaning t₂ ts Assert Read Assert Address Assert Request Data Lines Assert Ready Lower Request Lower Ready Bus is needed for reading (not writing) Indicates where bytes will be written Request read to address on address lines Read data (requires several cycles) Acknowledges read request, bytes placed on data lines Request signal no longer needed Release bus
19. 19. We pointed out that I/O buses do not need separate address
lines. Construct a timing diagram similar to Figure 7.11 that describes
the handshake between an I/O controller and a disk controller for a
write operation. (Hint: You will need to add a control signal.)
Transcribed Image Text:19. 19. We pointed out that I/O buses do not need separate address lines. Construct a timing diagram similar to Figure 7.11 that describes the handshake between an I/O controller and a disk controller for a write operation. (Hint: You will need to add a control signal.)
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