sample final exam questions

1. What is the modulo of the circuit below? 2. Make a table of the count sequence. 3. A BCD counter can assume____discrete state. 4. A BCD counter can divide its input frequency by____. 5. A four-bit binary counter contains the number 0100. Nine inpulse occur. The new counter state is_____. 6. Design a 4-bit down counter.

please show work included   4. If a 6-bit binary number is used to represent an analog value in the range from -63 to 126, what is the accuracy of the system? In other words, if the binary number is incremented by one, how much change does it represent in the analog value?

Procedure: 1. Design an even/odd parity generator for 4-bit data. 2. Design a parity checker circuit for a 4-bit data. 3. Design a logic circuit for a 3-bit message to be transmitted with an even parity bit. 4. Four data bits are to be transmitted. Design a parity bit generator to give an o/p of 'l' if the number of logic l's in the message is: (i) odd; (ii) even.

PLEASE HELP WITH PARTS A,B,C

1. Implement the following Boolean function by using 4x1 multiplexer. F(A,B, C, D) = Em(1,3,5,6,8,11,14) 2. Construct a logical circuit of 64 x 1 multiplexer using 4 × 1 multiplexer. 3. Construct a priority encoder circuit of 8x3. 4. Design a 4-bit BCD to Gray Code Converter by using Programmable Array logic.

Decoder circuit as shown in the following Figure. if A is LSB and C is MSB, the output expression F= YO Y Y, Y, D. Y. Decoder O a. B' O b. C O'c.B O d. C

parity generator design, construct and test a circuit that generates an even parity bit ffrom four messages bits . use XOR gates. adding one more XOR gate, expand the circuit so that it generates an odd parity bit also.

5. The following diagram represents a four-bit ring counter. Assuming a starting state of Q3 = 1 and Q₂ = Q₁ = Qo= 0, complete the timing diagram. Explain how this counter works. CLK 23 2₂ 2₁ 20 D CLK Q3 D 22 >CLK D 2₁ >CLK D CLK Lot

New Solution

Design and draw a 3 bit Gray code synchronous counter with the state diagram shown below [14 marks] State diagram for a 3-bit Gray code counter

Perform the following functions:a. What will be the parity of the data signal to send as even parity:10100111001b. (0101)BCD = (---?---)2 = (---?---)Excess-3 = (---?---)Grayc. How to represent following numbers in signed representation:1. (-78)102. (-19)10

Let A = ajao and B = b¡bo be two-bit binary numbers. A and B can take on values from 0 to 3 (for example, A = 2 when a1ao = 10. Let C be a two bit binary number whose value equals the magnitude of the difference A – B. We have C = c1c0 = |A – B|. (This means that if B is larger than A then you consider B-A.) You are to design a circuit which accepts A and B (i.e., a¡ aob¡bo) as inputs and outputs the result C = c¡c0. The circuit thus has four inputs and two outputs. For example, the circuit should output c1co = 10 when ajao = 01 and bibo = 11 (C = 2 when A = 1 and B = 3). - Your pre-lab needs to include all items requested in the following steps (plus those requested in the pre-lab handout): 1. After reading through the complete lab, write a description of the expected behavior of the system you will design. 2. Draw a truth table describing the behavior of the circuit. The truth table should show the inputs: aj aobibo (in this order) and the outputs: c1Co · 3. Write the canonical SOP…