VLSI Design_hw3

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NJIT VLSI Design – I Homework – III Prepared for Pro. D. Misra September 23, 2021 Objectives 1. Compare the rising and falling delays for inverter of 180nm and 65nm processes with two different loads .

NJIT 2. Calculate the critical voltages (VOL, VOH, VIL, VIH) on the voltage transfer characteristics and find the noise margins of the resistive load inverter circuit. 3. Sketch the side view (cross-section) of the 2 input NAND gate. 4. Find the values of VIL, VIH, VOL, and VOH that give best noise margins, and find what are these high, (NMH) and low (NML) noise margins from novel inverter transfer charlatanistic. 5. Sketch a transistor-level schematic for Boolean function that given in question 5. Q1 : Loaded inverter 1.1. Inverter with single inverter 65nm HSPICE Netlist

NJIT WV rustles * Aseel Zeinati akz4@njit.edu sep20/21 *Transient Analysis inverter with single inverter 65nm * ........................... * parameters and models * .......................... .include '/afs/cad/u/a/k/akz4/model_vlsi/model65nm.sp' .option scale = 32.5n .option post .temp 65 * ........................... *subcircuits * ........................... .global vdd gnd .subckt inv a y n=4 p=8 M1 y a gnd gnd nmos W='n' L=2 M2 y a vdd vdd pmos W='p' L=2 .ends * ........................... *simulation netlist * ........................... Vdd vdd gnd 1 Vin a gnd pulse 0 1 0ps 100ps 100ps 500ps 1000ps X1 a y inv * device under test X2 y b inv * load * ........................... *stimulus * .......................... .tran 100ps 1000ps *rising prop delay .measure tpdr + trig v(a) val=0.5 fall=1 + targ v(y) val=0.5 rise=1 *falling prop delay .measure tpdf + trig v(a) val=0.5 rise=1 + targ v(y) val=0.5 fall=1 .end

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NJIT 1.2. Inverter with four inverters 65nm HSPICE Netlist FIGURE 1 Transient analysis of an inverter with a single inverter as load in 65nm process

NJIT WV rustles * Aseel Zeinati akz4@njit.edu sep20/21 *Transient Analysis inverter with four inverters 65nm * ........................... * parameters and models * .......................... .include '/afs/cad/u/a/k/akz4/model_vlsi/model65nm.sp' .option scale = 32.5n .option post .temp 65 * ........................... *subcircuits * ........................... .global vdd gnd .subckt inv a y n=4 p=8 M1 y a gnd gnd nmos W='n' L=2 M2 y a vdd vdd pmos W='p' L=2 .ends * ........................... *simulation netlist * ........................... Vdd vdd gnd 1 Vin a gnd pulse 0 1 0ps 100ps 100ps 500ps 1000ps X1 a y inv * device under test X2 y b inv X3 y b inv X4 y b inv X5 y b inv * ........................... *stimulus * .......................... .tran 100ps 1000ps *rising prop delay .measure tpdr + trig v(a) val=0.5 fall=1 + targ v(y) val=0.5 rise=1 *falling prop delay .measure tpdf + trig v(a) val=0.5 rise=1 + targ v(y) val=0.5 fall=1 .end

NJIT 2.1. Inverter with single inverter 180nm HSPICE Netlist FIGURE 2 Transient analysis of an inverter with four inverters as load in 65nm process

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NJIT WV rustles * Aseel Zeinati akz4@njit.edu sep20/21 *Transient Analysis inverter with single inverter 180nm * ........................... * parameters and models * ........................... .include '/afs/cad/u/a/k/akz4/model_vlsi/model180nm.sp' .option scale = 90n .option post .temp 65 * ........................... *subcircuits * ........................... .global vdd gnd .subckt inv a y n=4 p=8 M1 y a gnd gnd nmos W='n' L=2 M2 y a vdd vdd pmos W='p' L=2 .ends * ........................... *simulation netlist * ........................... Vdd vdd gnd 1.8 Vin a gnd pulse 0 1.8 0ps 100ps 100ps 500ps 1000ps X1 a y inv * device under test X2 y b inv * load * ........................... *stimulus * .......................... .tran 100ps 1000ps *rising prop delay .measure tpdr + trig v(a) val=’1.8/2’ fall=1 + targ v(y) val=’1.8/2’ rise=1 *falling prop delay .measure tpdf + trig v(a) val=’1.8/2’ rise=1 + targ v(y) val=’1.8/2’ fall=1 .end

NJIT 2.2. Inverter with four inverters 180nm HSPICE Netlist FIGURE 3 Transient analysis of an inverter with single inverter as load in 180nm process

NJIT WV rustles * Aseel Zeinati akz4@njit.edu sep20/21 *Transient Analysis inverter with four inverter 180nm * ........................... * parameters and models * .......................... .include '/afs/cad/u/a/k/akz4/model_vlsi/model180nm.sp' .option scale = 90n .option post .temp 65 * ........................... *subcircuits * ........................... .global vdd gnd .subckt inv a y n=4 p=8 M1 y a gnd gnd nmos W='n' L=2 M2 y a vdd vdd pmos W='p' L=2 .ends * ........................... *simulation netlist * ........................... Vdd vdd gnd 1.8 Vin a gnd pulse 0 1.8 0ps 100ps 100ps 500ps 1000ps X1 a y inv * device under test X2 y b inv X3 y b inv X4 y b inv X5 y b inv * ........................... *stimulus * .......................... .tran 100ps 1000ps *rising prop delay .measure tpdr + trig v(a) val=’1.8/2’ fall=1 + targ v(y) val=’1.8/2’ rise=1 *falling prop delay .measure tpdf + trig v(a) val=’1.8/2’ rise=1 + targ v(y) val=’1.8/2’ fall=1 .end

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NJIT 3. Compare the rising and falling delays Single load 65nm Four loads 65nm Single load 180nm Four load 180nm t pdf 11.5ps 25.2ps 30.3ps 59.3ps t pdr 20.3ps 37.7ps 44.5ps 82.4ps Q2 : Resistive Load inverter FIGURE 4 Transient analysis of an inverter with fourinverter as load in 180nm process FIGURE 5 a table represent a different values of rising an falling delay of all processes

NJIT #claculate V OH Since the nMOS at cutoff mode when v in <v t0 then : V OH =V DD =5V #calculate V OL Since the nMOS at linear mode when v in -v t0 > V OL then : I D =  ((V in -V t0 )-V OL /2)V OL I D =(V DD -V OL )/R  =40  A/V 2 V in =V OH =V DD =5V V t0 =0.8V R=200k   ((V in -V t0 )-V OL /2)V OL =(V DD -V OL )/R 4V OL 2 -34.6V OL +5=0 V OL =8.5v >V DD this is not the right value! V OL =0.147V #calculate V IL Since the nMOS at saturation mode when v in -v t0 < V out then : I D =0.5  (V IL -V t0 ) 2 0.5  (V IL -V t0 ) 2 = (V DD -V OL )/R Take the derivative with respect of V IL − 1 R dV out dV IL = β ( V IL − V t 0 ) dV out dV IL =− 1 V IL =0.925V #calculate V IH Since the nMOS at linear mode when v in -v t0 > V out then : I D =  ((V IH -V t0 )-V out /2)V out I D =(V DD -V out )/R  ((V IH -V t0 )-V out /2)V out =(V DD -V out )/R Take the derivative with respect of V IH − 1 R dV out dV IH = β ¿ V IH =0.675+V out Substetud V IH in I D =  ((V IH -V t0 )-V out /2)V out with (0.675+V out ) 0.5 V out 2 -0.625=0 V out =1.118V at V IH

NJIT V IH =1.793V NM H =V OH -V IH =3.207V NM L =V IL -V OL =0.778V Q3 : Cross-section of the 2 input NAND gate Q4 : Novel inverter transfer charlatanistic V OH =1.2V V OL =0.15V V IL =0.3V To find V IH we know that the slop of the line is -1 (1.2-0.15)/(0.3-V IH ) V IH =1.05V FIGURE 6 Cross-section X to X’ FIGURE 7 Cross-section Z to Z’

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