VLSI Design_hw2

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NJIT VLSI Design – I Homework – II Prepared for Pro. D. Misra September 16, 2021 Objectives 1. Determine device parameters from a Measured voltage and current data for an n-channel MOSFET at room temperature.

NJIT 2. Perform a DC analysis of cMOS inverter by drawing a transfer characteristic while varying the width and length of the gate of both the transistors in the inverter. 3. Explain your results of transfer characteristics then suggest the advantages and disadvantages of the extreme cases. 4. Find the voltages at each of the nodes in given circuit. 5. Realize a Boolean functions using CMOS technology with the minimum possible number of transistors. Q1 : Device Parameters Measured voltage and current data for an n-channel MOSFET at room temperature are given below. Determine (a) the threshold voltage V T0 =1.43V , (b)  =41.846A/V 2 (c) the body effect coefficient  =0.8301 and (d) channel length modulation coefficient  =0.1 . Assume |2  b | = 0.60 V. V GS (V) V DS (V) V SB (V) I D (μA) 2 5 0 10 5 5 0 400 5 5 -3 280 5 8 0 480 Using the data from the table, we will set up equations containing the unknowns of interest. Let us first assume the region of operation. Since V DS >V GS -V T0 in all data points that means that the transistor is in saturation mode So we will use EQ1 which calculate the channel length modulation coefficient. I D = ❑ 2 (V GS -V TO ) 2 (1+V DS  ) …………………………………………………………….. ………………. EQ1 Using this assumption, the first two data points with the last one give us the following equations: 20= ❑ 2 (2-V TO ) 2 (1+5  ) ………………………………………………………………..…………….. …. . 1 400= ❑ 2 (5-V TO ) 2 (1+5  ) …..…………………………………………………………..…………….. ….. 2 Table 1 Measured voltage and current data for an n-channel MOSFET at room temperature

NJIT 480= ❑ 2 (5-V TO ) 2 (1+8  ) ………………………………………………………………..……………. …. 3 Let’s divide equation 3 by equation 2 : 1.2 = 1 + 8 λ 1 + 5 λ  = 0.1 divide equation 2 by equation 1 : 40 = (5-V T0 ) 2 /(2-V T0 ) 2 39 (V T0 ) 2 -150 V T0 +135=0 V T0 =2.4V (this is couldn’t be the value of V T0 since I D =10  A at V GS =2V then 2V> V T0 ) V T0 = 1.43V (this is the value of the threshold voltage) Then  = 41.846 A V 2  = √ 2 q ❑ si N A C ox ……………………………………………………………..…………………. ……. EQ2  b = kT q ln N A ¿ ……………………………………………………………..…………………. ……. EQ3 0.3= 1.38 × 10 − 23 × 300 1.602 × 10 − 19 ln N A 1.45 × 10 10 N A = 1.595 × 10 15 cm − 3 Q b = √ 2 q ❑ si N A ……………………………………………………………..……………..….. ……. EQ4 Q b = 2.327 × 10 − 8 c

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NJIT V T0 =2  + Q b /C ox …………………………………………………………..……………………. …. EQ5 C ox =2.8036 × 10 -8 F/cm 2  =0.8301 Q2 : cMOS Inverter Simulate the following circuit (Figure 1) in HSPICE using the 0.18μm process transistor models. The device sizes for the nMOS and pMOS devices are specified below. Use the source and drain areas in your simulation. Perform a DC analysis by drawing a ‘transfer characteristics,’ (V A vs V Y ) where you plot three different curves by varying the width and length of the gate of both the transistors as shown below. i. (W/L)n=2.0  m/0.18  m and (W/L)p=4.0  m/0.18  m ii. (W/L)n=4.0  m/0.18  m and (W/L)p=0.4  m/0.18  m iii. (W/L)n=0.4  m/0.18  m and (W/L)p=4.0  m/0.18  m Explain your results. Suggest the advantages and disadvantages of the extreme cases. HSPICE Netlist FIGURE 1 cMOS

NJIT WV rustles * Aseel Zeinati akz4@njit.edu sep04/21 * Inverter DC analysis * ........................... * parameters and models * ............................ .include '/afs/cad/u/a/k/akz4/model_vlsi/model180nm.sp' .include '/afs/cad/u/a/k/akz4/sep12/hspice/data_width_inv.gz' .option post .temp 65 * ........................... *simulation netlist * ........................... Vdd vdd gnd 1 Va a gnd 1 .param Wn=2u .param Wp=4u .param Sn='Wn*0.45u' .param Dn='Wn*0.27u' .param Sp='Wp*0.27u' .param Dp='Wp*0.45u' Mn y a gnd gnd NMOS W='Wn' L=0.18u AD=Dn AS=Sn Mp y a vdd vdd PMOS W='Wp' L=0.18u AD=Dn AS=Sp * ........................... *stimulus * .......................... .dc Va 0 1 0.05 sweep data=data_inv .end * data file for different width of nMOS and pMOS in inverter .data data_inv Wn Wp 2.0u 4.0u 4.0u 0.4u 0.4u 4.0u .enddata

NJIT The rustles in Figure 1 show that the device is an inverter. i. (W/L)n=2.0  m/0.18  m and (W/L)p=4.0  m/0.18  m shown by the middle curve which is unskewed inverter where  p =  n , since  n =2  p as the text book assume, then r i =  p /  n =1. An unskewed inverter has equal noise margins, which is maximize immunity to arbitrary noise source. ii. (W/L)n=4.0  m/0.18  m and (W/L)p=0.4  m/0.18  m shown by the blue curve on the right where r ii =0.05<1 so the inverter is LO- skewed. Which has weaker pMOS transistor, strong nMOS and thus a lower switching threshold. Reduce the pMOS transistor area it also reduce input capacitance which in turn reduce power consumption. iii. (W/L)n=0.4  m/0.18  m and (W/L)p=4.0  m/0.18  m shown by the red curve on the left where r iii =5>1 so the inverter is HI-skewed. Which has strong pMOS transistor, weaker nMOS and thus a higher switching threshold. Skewed inverter is a noise-tolerant high-performance inverter with low power consumption. It also has noise immunity, but sometimes cause hot electron degradation . Q3 : Pass transistors Find the voltages at each of the nodes, A, B, C, D, E and F below, assuming that all the nodes are initially at 2.5 V. Use the following circuit parameters. V dd = 5 V, V tn = 0.5 V and |V tp | = 1.5 V. FIGURE 2 DC transfer charactaristics of cMOS inverter with different width and length of gate

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NJIT A=5.0 V B=4.5 V C=4.5 V D=0.0 V E=1.5 V F=5.0 V Q4 : Boolean functions Realize the following functions using CMOS technology with the minimum possible number of transistors. Assume that only the true (uncomplemented) variables are available. FIGURE 3 Q3 circuit