10.1.3 Practice Questions

Write VHDL code for a modulo-13 counter (counting sequence is 010, 110, …. 1210). The counter has the following features: a synchronous Active High Reset a value R can be loaded into the counter, using the signal Ld (Load) The signal Ld is active High Draw the schematic of your counter, showing the inputs and outputs. Show the number of bits for R, Q (output of the counter), Ld.

Need a solufor number 2

Modify the Laser Circuit FSM to output x for 25 ns, assuming Tclk = 5 ns. Draw the new State Diagram. How many states have the new State Diagram? Write VHDL code showing separate “blocks” for the next state decoder, memory, and output decoder. Add an Asynchronous Reset active Low.

Write VHDL code for an n-bits register (n can be 4, 8, 16, …) with the Synchronous Reset Active High, and Load Input Active High.

Q3. b) Suppose you want to transmit the 10-bit message [101101101] by Pulse code Modulation (PCM). Using clearly labeled diagrams, show the encoding the bit sequence using the following PCM waveform types: i) Bipolar RZ Signal ii) RZ-AMI iii) Bi – o - L iv) Delay modulation

Write VHDL code for an n-bits register (n can be 4, 8, 16, …) with the Synchronous Reset Active Low, and Load Input Active Low.

TRUE OR FALSE: More than one output of a BCD-to-7 segment decoder/driver can be active at one time.

4. A data signal with bipolar voltage levels is shown below. The decision threshold is 0 volts. The logic levels are +1 volt for logic 1 and -1 volt for logic 0. Noise with the P.D.F. shown corrupts the signal. Find the probability of error at some instant of time on the condition that logic 0 is sent. LOGIC 1 +1 VOLT -2 1/2 دمت ~IN kla THRESHOLD +2 NOISE P.D.F. -I VOLT. LOGIC 0

true or false

What are the potential effects of "write amplification" on SSDs?

Assume the baud rate equals bits per second. How long is a bit for a 9600 baud modem? A) 9600 B) 104 us C) 1.04 ns D) 9.6 ns