Module 10- Assignment

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School

Ashford University *

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CIS665

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Electrical Engineering

Date

Apr 3, 2024

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docx

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3

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Module 10 - Assignment 1. Explain the difference between a serial and a parallel bus. Why would you choose one mode of transfer over the other? Give examples of how each is used and why. ● Parallel buses require more lines, but can transfer data in blocks and can be faster. ● Parallel bus must align the clock, and clock skew can be a problem unless length is short. ● Asynchronous bus uses a handshaking protocol for coordinating usage rather than a clock; can host a wide variety of devices of different speeds ● For internal buses (lines on the CPU), buses are parallel. ● For system buses (lines to memory, controllers, etc), normally parallel, but can be serial. ● For buses to thing like disk drives, used to be parallel (PATA parallel SCSI), now more serial (SATA, serial SCSI) ● External buses (usb, firewire, network) are serial. 2. What are RAID 0, RAID 1, RAID 5, and RAID 10? Give examples of why you would use each of these. Which are faster, and why? Which of these give you greater reliability and why? What is hot swapping, and has does it impact reliability? RAID 0 No redundancy (“AID”?) Just stripe data over multiple disks But it does improve performance RAID 1: Mirroring N + N disks, replicate data Write data to both data disk and mirror disk On disk failure, read from mirror 3. Be able to give a simple example of Bus Mastering using one device and the CPU controlling the System Bus. How are the BR, BG, and Int signals used? 1 – CPU controls memory access
2 - Controller Bus Request (BR) is raised. 3 – When ready, CPU raises Bus Grant (BG) 4 – When done, Controller lowers BR 5 – CPU lowers BG 6 – Controller signals interrupt to CPU 4. What lines are generally part of the System Bus? A parallel bus that simultaneously transfers data in 8-, 16-, or 32-bit channels and is the primary pathway between the CPU and memory. For system buses (lines to memory, controllers, etc), normally parallel, but can be serial. 5. Why does the kernel use kernel memory and not user memory when communicating with the System Bus using DMA memory. 6. What is DMA, and how does it work. A mechanism that provides a device controller with the ability to transfer data directly to or from the memory without involving the processor OS provides starting address in memory I/O controller transfers to/from memory autonomously Controller interrupts on completion or error 1. The processor sets up the DMA by supplying the identity of the device, the operation, the memory address (source or destination), and the number of bytes to transfer 2. The DMA controller starts the operation on the device When the data is available, it transfers the data The DMA controller supplies the memory address for the R or W. If the request requires more than one transfer, the DMA controller generates the next memory address, and initiates the next transfer A DMA unit can complete an entire transfer, which may be thousands of bytes in length, without bothering the processor 3. When the DMA transfer is complete, the controller interrupts the processor 7. Contrast DMA with interrupts with polling.
Polling and interrupt-driven I/O CPU transfers data between memory and I/O data registers Time consuming for high-speed devices 8. Know what disk dependability is, and how to apply the concept correctly. 9. What is Amdahl's law, and why is it important? Don’t neglect I/O performance as parallelism increases compute performance Example Benchmark takes 90s CPU time, 10s I/O time Double the number of CPUs/2 years I/O unchanged The parallel revolution needs to come to I/O
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