CPSC3300_Exam1_FallB (1)

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Apr 3, 2024

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Name: __________________________________________ CPSC 3300 – Exam 1 (70 points) (CLOSED BOOK – No notes or calculators) Fall-B 2022 (ARM Instruction Set Reference is attached for your use.) 1. (8 points) A byte of memory contains the 8-bit binary code: 10000111. What decimal number does this code represent in each of the following number systems. a. Unsigned:______________ b. Two’s Complement:_________________ 2. (8 points) A 5-bit CPU performs the operation (10) 10 – (14) 10 using two’s complement arithmetic. Show how the operation is performed and determine the 5-bit result (in binary) and the values of the zero (Z), sign (N), carry (C) and overflow (V) flags. Result = ____________________ Z =___ N =___ C =___ V =___ 3. (10 points) Write a logic expression that represents function F(A,B,C) defined in the following truth table . F(A,B,C) = ________________________________________________ A B C F(A,B,C) 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 0 1 1 1 0

4. (10 points) Given the assembler directives below, complete the table showing each byte that will be stored in memory and where. Assume this code is in the code section and begins at address 0x100. Use the same endian-ness as the default for our processor. In the table, write each label in the line corresponding to the address assigned to that label. Write each address as a 3-digit hexadecimal number and each data byte as a 2-digit hexadecimal number – omit the “0x” .) Bob dcd -2, 0x45546776 Sue dcb 12, 0x12, -12 Pat dcd 0x98765432 Label Memory Address (in hex) Byte Stored (in hex) Bob 100 101

5. (10 points) Given the ARM program below, assume the data values are those listed in the assembler directives. Determine the values loaded into the indicated registers by each instruction, and enter those values on the lines provided as 8-digit hexadecimal numbers. (You might consider sketching the data memory to help visualize it.) In this case, the DATA area begins at address 0x20000000. AREA Data1, DATA A1 DCD 0x87654321, 0x4 A2 DCB 0x62, 0xE4 A3 DCB 0x17, 0xB5 A4 DCD 0xFEDCBC98,0x09080706 AREA Code1,CODE ;Register contents after instruction: Main: LDR R0,=A1 ; R0 =_____________________ ____________ LDR R1,[R0] ; R1 =____________ ________ _____________ LDRB R2,[R0,#4] ; R2 =_________________ R0=________ _______ LDR R3,=A3 ; R3 =_____________ ______________ ______ LDRH R4,[R3],#2 ; R4 =__________________R3= ______________ MOV R5,#4 ; R5 =__________________ _________________ LDR R6,[R3,R5] ; R6 =________________ R3= __ ___________

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6. (12 points) Write a short sequence of instructions to perform the calculation shown below, where all operands are 32-bit signed integers. Assume that values have previously been assigned to the three variables. H = 5 − ( H + J ) ( J ∗ K ) AREA D0, DATA H SPACE 4 J SPACE 4 K SPACE 4

7. (12 points) Three 400-integer arrays are stored in the data area as shown below. Write a short ARM assembly language program to compute Ary1[K] = Ary2[K] – Ary3[K] + K; for values of K increasing from 0 to 399. Use a register for variable K, rather than a memory variable. AREA Data1,DATA Ary1 SPACE 400*4 ;400 32-bit integers Ary2 SPACE 400*4 ;400 32-bit integers Ary3 SPACE 400*4 ;400 32-bit integers

Cortex-M4 Thumb-2 Instruction Set Summary <Operand2> may be one of the following: #imm8 One byte, zero-extended to 32 bits (a few other formats can also be produced) Rm Normal register operation Rm, <LSL|LSR|ASR|ROR> #imm5 Register operation with constant shift Rm, RRX Register operation with rotate right with extend <S> (instruction mnemonic suffix) => Update the condition flags after the instruction has executed MOV{S} Rd, <Operand2> Move Rd = Operand2 MVN{S} Rd, <Operand2> Move not Rd = 0xFFFFFFFF EOR Operand2 MOV Rd, #<imm16> Move wide Rd = imm16 (zero-extended) MOVT Rd, #<imm16> Move top Rd[31:16] = imm16, bits Rd[15:0] are unaffected ADD{S} Rd, Rn, <Operand2> Add Rd = Rn + Operand2 ADD Rd, Rn, #<imm12> Add wide Rd = Rn + Imm12 ADC{S} Rd, Rn, <Operand2> Add with carry Rd = Rn + Operand2 + Carry SUB{S} Rd, Rn, <Operand2> Subtract Rd = Rn - <Operand 2> SBC{S} Rd, Rn, <Operand2> Subtract with carry Rd = Rn – Operand2 - (1 - Carry) SUB Rd, Rn, #<imm12> Subtract wide Rd = Rn - imm12 RSB{S} Rd, Rn, <Operand2> Reverse subtract Rd = <Operand 2> - Rn RSC{S} Rd, Rn, <Operand2> Reverse subtract with carry Rd = Operand2 – Rn – (1 - Carry) MUL{S} Rd, Rm, Rs Multiply Rd = Rn * Rm Returns the 32 least significant bits of the result MLA Rd, Rm, Rs, Rn Multiply and accumulate Rd = (Rn + (Rm * Rs)) Returns the 32 least significant bits of the result MLS Rd, Rm, Rs, Rn Multiply and subtract Rd = (Rn - (Rm * Rs)) Returns the 32 least significant bits of the result UMULL RdLo, RdHi, Rm, Rs Multiply unsigned long, 64 bit result SMULL RdLo, RdHi, Rm, Rs Multiply signed long, 64 bit result SDIV Rd, Rn, Rm Signed division Rd = Rn/Rm (0x80000000 / 0xFFFFFFFF = 0x80000000, Rn / 0 = 0) UDIV Rd, Rn, Rm Unsigned division Rd = Rn/Rm (Rn / 0 = 0) ASR{S} Rd, Rm, <Rs|#imm5> Arithmetic shift right, canonical form of MOV{S} Rd, Rm, ASR <Rs|#imm5> LSL{S} Rd, Rm, <Rs|#imm5> Logical shift left LSR{S} Rd, Rm, <Rs|#imm5> Logical shift right ROR{S} Rd, Rm, <Rs|#imm5> Rotate right RRX{S} Rd, Rm Rotate right with extent, uses Carry as a 33rd bit CMP Rn, <Operand2> Same as SUBS Rd, Rn, <Operand2>, but result not written to Rd, only condition flags are updated CMN Rn, <Operand2> Rn + <Operand2> TST Rn, <Operand2> Rn AND <Operand2> TEQ Rn, <Operand2> Rn EOR <Operand2> AND{S} Rd, Rn, <Operand2> Bitwise AND, Rd = Rn AND <Operand2> ORR{S} Rd, Rn, <Operand2> Bitwise OR, Rd = Rn OR <Operand2> EOR{S} Rd, Rn, <Operand2> Bitwise Exclusive-OR. Rd = Rn EOR <Operand2> ORN{S} Rd, Rn, <Operand2> Or not, Rd = Rn OR NOT <Operand2> BIC{S} Rd, Rn, <Operand2> Bit clear, Rd = Rn AND NOT <Operand2> B <label> Unconditional jump BL <label> R14 = address of next instruction, then jump to label BX Rm Branch and exchange (jump to address in Rm), use it to return from a function (BX LR) BLX Rm R14 = address of next instruction, then jump to Rm Bcc <label> Conditional jump, where cc is one of {EQ,NE,GE,GT,LE,LT,HS,HI,LS,LO,VS,VC,CS,CC,MI,PL} <Address> can be one of the following Example Action [Rn] LDR R0,[R1] R0 = [R1 + 0] [Rn {, #<-imm8|+imm12>}] LDR R0, [R1, #8] R0 = [R1 + 8] [Rn {, #<+-imm8>}]! LDR R0, [R1, #8]! R1 = R1 + 8, R0 = [R1] [Rn], #<+-imm8> LDR R0, [R1], #4 R0 = [R1], R1 = R1 + 4 [Rn, Rm {, <LSL #0-3>}] STR R0, [R1, R2, LSL #2] R0 = [R1 + (R2 * 4)] LDR Rd, <Address> Load 32 bit word from memory LDRH Rd, <Address> Load 16 bit half-word from memory

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LDRSH Rd, <Address> Load signed 16 bit half-word from memory LDRB Rd, <Address> Load 8 bit byte from memory LDRSB Rd, <Address> Load signed 8 bit byte from memory STR Rd, <Address> Store 32 bit word to memory STRH Rd, <Address> Store 16-bit halfword to memory STRB Rd, <Address> Store 8-bit byte to memory LDR Rd,=Label Pseudo-Op: Load Rd with 32-bit address/constant equivalent to Label LDR Rd,=Constant Pseudo-Op: Load Rd with 32-bit constant PUSH <reglist> Push registers onto stack pointed to by SP, decrement address before each store; lowest-numbered register to the lowest memory address POP <reglist> Restore registers from stack, increment address after each load. Be careful with registers SP and PC. LDM{IA|IB|DA|DB} Rn{!}, <reglist> Load/store multiple, can transfer any list of registers, ! will update Rn to point to the address after/before the last register STM{IA|IB|DA|DB} Rn{!}, <reglist> IA = increment after (default), IB = increment before, DA = decrement after, DB = decrement before (Action on address)