HW 3 - Google Docs

Q3 Figure Q3 shows a functional block diagram of a digital circuit. Уз y2 Yo X3 X2 C3 C2 FA FA FA FA $3 $2 So V N (overflow) (negative) (zero) Figure Q3 (a) Name the circuit and explain the operation of the given FBD. (b) Discuss the importance of this circuit in digital hardware.

Please find the truth table for this circuit

HW Matlab 1) Create a variable fiemp to store a temperature in degrees Fahrenheit (F). Write m-file to convert this to degrees Celsius and store the result in a variable ctemp. The conversion factor is C = (F —32) * 5/9. 2) Write m-file to generate a matrix of random integers of size 100 by 100 their values between 15 to 80. 3) Free fall of objects is given by y =5mgt? where a is the acceleration, v is the velocity, y is the distance, m is the mass of the object, g is the gravitational acceleration. Plot the distance and velocity of the object for 15 seconds after its fall from rest (y = 0). Take m = 0.2 kg.

For the chip below, determine the selection S2S1S0 that will generate a 1 at the Y output for the input conditions: I = 1z16l5|4|3|21110 = 00000100. Assume the device is enabled to have normal operation. U3 74LS151 EO- S2 S1 SO 15 14 H13 12 I0 YNO- 100 O_001 111 O 010 1654 3210 HHHH H H HE

This QUESTION FROM ADVANCED DIGITAL SYSTEMS DESIGN course.

Please answer fast I'll rate you

In a simple, three-phase voltage-source inverter of the form shown in Fig. 8.18, the direct voltage va in the link is 550 V. The frequency of the inverter output is 200 Hz. Determine: (a) the rms value of the fundamental component of the output voltage, line to line and line to neutral, and (b) the rms value of the actual output voltage line to line and line to neutral.

(b) Using a synchronous binary counter as shown in Figure Q2(b), design and draw a counter to generate the following repeating sequences 2 to 14 repeatedly for a free running clock. If the circuit happens to enter any of the states 15 or 0 or 1, what are the next states of your circuit? A A Syn. Binary Counter Q3 Q2 Q₁ Qo →Asyn. clear Syn. load CLK D3 D₂ D₁ Do ↑↑↑↑

Please answer question 1C, 1D with details on why its true or false. Please make handwriting legible. Thank you