analog quiz 4

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1) DC offsets, bias currents Vin R1 www 1k www Ú1 R3 R2 www 4k OUT ww11. U2 R4 1k OUT R5 ww 1k Vout The bias characteristics for both amplifiers are VDCoffset = 4mV I bias = 2μA I¹ bias = 2μa a) Determine a value for resistor R3 such that the output voltage due to DC biases is zero.

b) For a class B power amplifier, show that the maximum efficiency is 78.5%. For a class B amplifier providing a 20V peak-to-peak signal to an 8 2 speaker and a power supply of Vee 15V, determine: i) ii) iii) c) %3D Input power Output power Circuit efficiency

6) Consider the following multistage amplifier. Draw the corresponding small signal model. Label, Vin, Vo1 and Vo. Do NOT make any approximations. Do NOT perform small signal analysis with this model. Just draw the small signal model. Show your work! Vin Vcc malli Q1 Re1 Vo1 Vcc ww1. Rc2 Q2 Re2 Vo

1.7. In a single transistor based amplifier (a) Source in a common source w/o degeneration is at DC ground but not AC ground (b) Source in a common source with degeneration is at AC ground but not DC ground (c) Input voltage is commonly connected to the gate (d) Drain in a common source w/o degeneration is at AC ground but not at DC ground 1.8. In a positive voltage system (all DC voltages in circuit >0V) (a) For a common gate amplifier, maximum small signal current occurs in saturation (b) Gate terminal is both DC ground and AC ground (c) Current gain of the common gate stage is approximately unity (d) Drain of a common drain NMOS based amplifier is connected to max voltage 1.9. In a single transistor based amplifier (a) Common source with degeneration is used to increase output impedance (b) Common source amplifier with degeneration does not provide phase inversion (c) The maximum intrinsic gain of basic CS amplifier w/o degeneration is independent of biasing condition (d) CG stage…

Among the three characteristics of a transistor amplifier, which region is normally employed for linear (undistorted) amplifiers? a. active region b. capital region c. saturation region d. cutoff region Choose correct answer

A field effect transistor (FET) A. Uses a forward bias p-n junction, B. Uses a high concentration emitter junction, C. Has a very high input resistance, D. Depends on flow of minority carrier. As compared to transistor amplifier JFET amplifier has A. Higher voltage gain, less input impedance, B. Less voltage gain, less input impedance, C. Less voltage gain, higher input impedance, D. Higher voltage gain, higher input impedance. The pinch off voltage is the voltage A. At which gate source junction breaks down, B. Which causes depletion regions to meet, C. The voltage applied between drain & source, D. Neither of these. O If properly biased JFET acts as A. Current controlled current source, B. Voltage controlled voltage source, C. Voltage controlled current source, D. Current controlled voltage source.

2) Draw the small signal model for the amplifier shown below. Do not make any approximations. Label Vin and Vo. Vdd Vdd Vdd R2 R4 R6 R1 Vo1 Vin2 Vo Vin R5 R3 R7

Please solve it.

Design a linear amplifier, based on a bipolar junction transistor 2N3904 in common emitter configuration. The supply voltage is 28V. The quiescent operating collector current for the amplifier should be around 10mA. The data sheet for the transistor shows that the DC current gain at this operating current is about 200. Draw the circuit diagram of your design. Label all the components in the circuit. Show all the voltages and currents that you use for calculations in your design. Label them using consistent naming convention.

Problem 3: The circuit below is a BJT common collector amplifier. Obtain expressions for both the voltage gain A, = You and the current gain A1 = put. Assume Vin » VBE. Vol (Power supply) To 2 Tin Ic 2 9m 2 Ic VT Rin B www. + vin -VBE RL B 1+³ V BE [te] IC VCE E Tout RL O Vin - VBE + Vout

help  with some explanation

Q1. Figure 1 shows a differential amplifier. Assume that all transistors are identical. 3=180, V₂=0.026 Vand VBE = 0.7V. a) b) c) Show that the d.c. bias current to the differential pairs is Iccs = 0.6 m.A. Calculate the d.c. voltages at the output terminals V1 and 12 Given that the input signals are V₁ = 4sin(wt) and V₁ = 2 sin(wt) in mV, find the a.c. voltage between Vo1 and Vo2- 5k0 9.6k0 +12 V 6k0 200411 01₁ Figure 1 I CCS 12k0 6k0 0411