Lesson_3_Lab_Combinational_Logic
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Chandler-Gilbert Community College *
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Course
120
Subject
Electrical Engineering
Date
Feb 20, 2024
Type
docx
Pages
5
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CSC/EEE120 – Lab 3
Topics:
Working with truth tables, minterm, maxterm, SOP and implementing the logic in circuits.
Submission:
Report uploaded to RioLearn; Please use copy/paste screenshots from LogicWorks for the sections requiring a diagram of a logic circuit.
1.
Given the following truth table Inputs
Output
Inputs
Output
A
B
C
Y
A
B
C
Y
0
0
0
0
1
0
0
0
0
0
1
0
1
0
1
0
0
1
0
0
1
1
0
1
0
1
1
1
1
1
1
0
a.
Write a minterm
Boolean expression for the truth table (3 points)
Y = A
’
BC + ABC
’
b.
Diagram a logic circuit (using LogicWorks) that will perform the logic in the truth table (4 points)
0
1
A
0
1
B
0
1
C
1
2.
Given the following truth table
Inputs
Output
Inputs
Output
A
B
C
Y
A
B
C
Y
0
0
0
1
1
0
0
0
0
0
1
0
1
0
1
1
0
1
0
0
1
1
0
0
0
1
1
1
1
1
1
0
a.
Write a sum-of-products Boolean expression for the truth table (3 points)
Y = A
’
BC + AB
’
C
b.
Diagram a logic circuit (using LogicWorks) that will perform the logic in the truth table (4 points)
0
1
A
0
1
B
0
1
C
1
2
3.
Given the following truth table
Inputs
Output
Inputs
Output
A
B
C
Y
A
B
C
Y
0
0
0
1
1
0
0
1
0
0
1
0
1
0
1
1
0
1
0
1
1
1
0
0
0
1
1
1
1
1
1
1
a.
Write a maxterm Boolean expression for the truth table (3 points)
Y = A
’
B
’
C
’
+ A
’
BC
’
+ A
’
BC + AB
’
C
’
+ AB
’
C + ABC
b.
Diagram a logic circuit that (using LogicWorks) will perform the logic in the truth table (4 points)
0
1
C
0
1
B
0
1
A
0
4.
Given the following truth table
Inputs
Output
Inputs
Output
A
B
C
Y
A
B
C
Y
0
0
0
0
1
0
0
1
0
0
1
1
1
0
1
0
3
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0
1
0
1
1
1
0
1
0
1
1
0
1
1
1
1
a.
Write a product-of-sums Boolean expression for the truth table (3points)
A'B'C+A'BC'+AB'C'+ABC'+ABC
b.
Diagram a logic circuit that (using LogicWorks) will perform the logic in the truth table (4 points)
0
1
A
0
1
B
0
1
C
1
5.
Write a truth table for a 3-input XOR gate. Remember that an odd number of 1s generate a 1 output
(4 points)
A
B
C
OUTPUT
0
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
1
6.
Given an OR gate and inverters, draw a logic diagram (circuit, using LogicWorks) that will perform the 2-input NAND function (4 points)
4
A'BC + AB'C
0
1
0
1
0
7.
Given an OR gate and inverters, draw a logic diagram (circuit, using LogicWorks) that will perform the 2-input AND function (4 points)
0
1
0
1
1
Report requirements
Insert the answers to the questions above in this document and submit as a PDF to RioLearn, or create a separate document with your answers for submission to RioLearn.
5
Related Questions
9:38....
89
Assignment 3_ECE 161.pdf
Assignment 3 (CLO 3)
ECE-161 Digital Logic Design
Deadline: Friday, May 10, 3:00 pm
Q.1
Design a binary multiplier to multiply two 4-bit numbers by utilizing AND gates and binary adders
in the design.
Q. 2
You are required to design a combinational logic circuit that takes two 4-bit numbers A and B
and a 1-bit input C. The circuit should function as an adder or a subtractor of the inputs A and B,
such that based on the input C it toggles between addition and subtraction. Assume that A>B.
Q.3
Design a combinational circuit based on the given three Boolean functions.
F₁(A,B,C)=(2, 4, 7)
F₂(A,B,C)=(0,3)
F3(A,B,C)=(0, 2, 3, 4, 7)
Implement the circuit using a decoder constructed with NAND gates and "NAND or AND" gates
connected to the decoder outputs.
Q.4
Construct a full adder utilizing two 4x1 multiplexers.
Q.5
Construct a circuit to implement the following truth table shown below.
SR
0 1
QQ'
1
0
1
0
0
1
1
1
Q
Q'
Q
용
Q.6
Design a BCD-to-decimal…
arrow_forward
3d. will give thumbs up
arrow_forward
Question 1
The static RAM 6264 is located starting at address 9E000 of the 8086 address space as shown in
the figure below.
a) What is the value of n? (see the notes below)
b) Show the address decoding circuitry adding external logic gates if necessary.
You can use the table below to analyze the address.
•
You must show all the connections to A, B, C, (G2A), (G2B), and G1.
• The address lines connected to the 6264 are indicated by n and the data lines are
indicated by d. You must also show the connection between the 74LS138 and the
6264 clearly on the figure below.
7415138
G2A
GZB
GI
S
Outputs
n
1888
CE
6264
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 AO
arrow_forward
H.W: Reduce the combinational logic circuit in Figure below to a
minimum form.
arrow_forward
Q2/A) Design 8x1 multiplexer using 2x1 multiplexer?
Q2 B)Simplify the Logic circuit shown below using K-map then draw the
Simplified circuit?
Q2/C) design logic block diagram for adding 12 to 5 using full adder showing
the input for each adder?
arrow_forward
3. Discussion:
1. Convert the gray code 01011001 to decimal number and show your work.
2. Convert the gray code 00101101 to binary number and show your work.
3. Design a 8-bit binary to gray code conversion circuit using logic gates and verify your design.
4. Design a 8-bit gray to binary code conversion circuit using logic gates and verify your design.
arrow_forward
Hi. Please may you give the solution to this question in a step by step form to help my understanding.
Both parts need to be completed in order to answer
arrow_forward
SEE MORE QUESTIONS
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Related Questions
- 9:38.... 89 Assignment 3_ECE 161.pdf Assignment 3 (CLO 3) ECE-161 Digital Logic Design Deadline: Friday, May 10, 3:00 pm Q.1 Design a binary multiplier to multiply two 4-bit numbers by utilizing AND gates and binary adders in the design. Q. 2 You are required to design a combinational logic circuit that takes two 4-bit numbers A and B and a 1-bit input C. The circuit should function as an adder or a subtractor of the inputs A and B, such that based on the input C it toggles between addition and subtraction. Assume that A>B. Q.3 Design a combinational circuit based on the given three Boolean functions. F₁(A,B,C)=(2, 4, 7) F₂(A,B,C)=(0,3) F3(A,B,C)=(0, 2, 3, 4, 7) Implement the circuit using a decoder constructed with NAND gates and "NAND or AND" gates connected to the decoder outputs. Q.4 Construct a full adder utilizing two 4x1 multiplexers. Q.5 Construct a circuit to implement the following truth table shown below. SR 0 1 QQ' 1 0 1 0 0 1 1 1 Q Q' Q 용 Q.6 Design a BCD-to-decimal…arrow_forward3d. will give thumbs uparrow_forwardQuestion 1 The static RAM 6264 is located starting at address 9E000 of the 8086 address space as shown in the figure below. a) What is the value of n? (see the notes below) b) Show the address decoding circuitry adding external logic gates if necessary. You can use the table below to analyze the address. • You must show all the connections to A, B, C, (G2A), (G2B), and G1. • The address lines connected to the 6264 are indicated by n and the data lines are indicated by d. You must also show the connection between the 74LS138 and the 6264 clearly on the figure below. 7415138 G2A GZB GI S Outputs n 1888 CE 6264 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 AOarrow_forward
- H.W: Reduce the combinational logic circuit in Figure below to a minimum form.arrow_forwardQ2/A) Design 8x1 multiplexer using 2x1 multiplexer? Q2 B)Simplify the Logic circuit shown below using K-map then draw the Simplified circuit? Q2/C) design logic block diagram for adding 12 to 5 using full adder showing the input for each adder?arrow_forward3. Discussion: 1. Convert the gray code 01011001 to decimal number and show your work. 2. Convert the gray code 00101101 to binary number and show your work. 3. Design a 8-bit binary to gray code conversion circuit using logic gates and verify your design. 4. Design a 8-bit gray to binary code conversion circuit using logic gates and verify your design.arrow_forward
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