ECE_Lab_02

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2060

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Electrical Engineering

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Feb 20, 2024

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Lab 02 – ModelSim and VHDL ECE 2060 Autumn 2023 Benjamin Lampe Cameron Jackson David Song Lab Group 34 F. Shehab Tues. 8:00AM Date of Experiment: 10/03/2023 Date of Submission: 10/20/2023

2 1. Introduction Measuring a gates waveform is important to validating it is performing correctly. If a gate does not perform correctly, be it either cannot produce the correct output or that it experiences some type 1 or type 2 errors. These incorrect performances can become devastating if the circuit is needed for something precise, such as an airport keeping track of plane locations. The purpose of this lab was too create a XOR gate block diagram and an AND gate VHDL file and then measure the waveforms for these gates. The next section details how the AND and XOR gates were created, as well as how the waveforms for those gates were recorded. The results and descriptions section contains the measured waveforms and short descriptions of the waveform behavior. The discussion section answers some questions related to the lab, including the differences of simulations used and the parts of the files used in the experiment. The conclusion section summarizes the results of the waveforms and how that relates to the purpose of the experiment. 2. Experimental Methodology The equipment needed for this lab is a computer with Quartus Prime software and ModelSim software. The group created a block diagram representing a XOR gate diagram. This block diagram can be seen in Figure 1 below.

3 Figure 1: XOR gate block diagram. From this block diagram, the group ran a ModelSim simulation to check the waveform of the circuit. The SW[0] input was set to a period of 50ps while SW[1] input was set to a period of 100ps. The waveform was recorded for 1000ps. Next, the group made a VHDL file to represent an AND gate. The VHDL file for this AND gate can be found on the next page in Figure 2. Figure 2: AND gate VHDL file. From this VHDL file, the group ran a ModelSim simulation to check the waveform of the circuit. The SW[0] input period was set to 50ps and the SW[1] input period was set to 100ps. The waveform was measured for 1000ps. 3. Results and Description Results

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4 Figure 3: XOR gate simulation.

5 Figure 4: AND gate simulation. 4. Discussion 1. What is the difference between a functional simulation and timing simulation? A functional simulation shows just the logic of a circuit, while a timing simulation shows the logic as well as showing delays in the circuit which can expose type 1 and type 2 errors. 2. Describe the steps to bring up a wave window in ModelSim. First the circuit must be compiled. After that the tools window in Quartus Prime should be opened and the run simulation option should be selected. From the run simulation

6 options, gate level simulation should be selected. In the ModelSim software, the view tab should be selected, and the wave option should be selected. To add elements to the wave window, the word tab should be opened, the circuit should be selected, and the inputs and outputs should be added to the wave window. 3. What are the two sections in a VHDL file? What are their functions? The first section of a VHDL file is the entity which contains the port statement which declares the inputs and the outputs of the design. The second section of the file is the architecture which will define hardware which is the behavior or implementation being expressed within the file. 4. What is the primary difference between a hardware description language and programming language? The primary difference is that it does not execute. Since the language is converted straight into hardware, there is no flow from top to bottom through the code. 5. Summary and Conclusions In the ModelSim and VHDL lab, the group was introduced to ModelSim which is a tool used to stimulate the designs we create in Quartus Prime. The group began by reopening the previously created XOR gate and then running the Gate Level Simulation to load the ModelSim. Upon verifying that the results from the ModelSim displayed what was expected, the team moved on to creating a new VHDL file of the AND gate by writing the provided code. This was then used to create a new symbol file. The group then created a new bdf file in which the VHDL AND gate

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7 symbol was connected to input and output pins. The project was then compiled and run through the Gate Level Simulation to test the AND gate. The group then verified the correctness with the same process as the XOR Gate. In conclusion, the team was able to successfully run the Gate Level Simulation for both the XOR Gate and the VHDL AND Gate. The group made sure to use the correct frequency for each of the inputs and create the correct waveform that was desired. The group was then able to use the results of these displayed graphs to verify the expected output given the different possible outputs. The team was able to conclude the lab successful due to provided graphs and verification of checkpoints from lab monitor.