CEG 2138 Lab1

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School

University of Ottawa *

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Course

2138

Subject

Electrical Engineering

Date

Feb 20, 2024

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pdf

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Uploaded by EarlTarsier738

Lab 1 CEG 2138 - Computer Architecture I Fall 2022 School of Electrical Engineering and Computer Science University of Ottawa September 22nd, 2022 Index Figure 1.0 - Theoretical Truth Table…………………………………………………………………….3 Figure 1.1 - Experimental Circuit………………………………………………………………………..4 Figure 2.0 - Function of the Full Adder…………………………………………………………………4

Figure 3.0 - Circuit Part III.I in Quartus…………………………………………………………………5 Figure 3.1 - Functional Simulation………………………………………………………………………5 Figure 3.2 - Timing Simulation…………………………………………………………………………..6 Figure 3.3 - Circuit Part III.II in Quartus………………………………………………………………...7 Theoretical Part In this lab, we are designing a simple circuit which we assume to be a full adder. The importance of this type of circuit is the fact that it is a very important basis for being able to create more complex circuits in the future. The principle of a full adder of this sort is to be able 2

to “hold” a binary digit in its flip-flop and then “give it back” to the circuit to be able to add and increase the number (+1). This being said, an adder of this sort has many drawbacks, to name a few, the adder can only increase by a step of 1, and cannot subtract (hence the name “adder”). Regardless, this is a very important fundamental circuit which isn’t too complicated to grasp while still having interesting results. In this lab, we weren’t asked to solve a problem, we were rather asked to follow a series of instructions to experimentally verify our theoretical truth table (Fig. 1.0) of the experimental circuit (Fig. 1.1) and show that they correlate. This circuit consists of 3 inputs, 2 XOR gates, 2 AND gates, one OR gate and 2 outputs. We will use these gates in Quartus to prove our design. Figure 1.0 - Theoretical Truth Table 3

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Figure 1.1 - Experimental Circuit Source: Lab Instruction Manual Design Referring back to Figures 1.0 & 1.1, we get a decent understanding of the design of this circuit. The circuit has upgraded itself from its predecessors, the half-adder. Hence the name full adder. The full adder's main difference from the half adder is the fact that a full adder has one extra input, allowing it to perform two times more operations than the half-adder! A quick breakdown of the circuit allows us to have a better understanding of its inner workings. The equation for the circuit can be seen in (Fig 2.0). Figure 2.0 - Function of the Full Adder Rewritten for legibility: 𝑆 = (? ⊕ ?) ⊕ ?𝑖?) ???? = ?? + ?𝑖?(? ⊕ ?) 4

Simulation and Verification of Real Implementation Now that we know what to expect, let’s build the circuit as per Part III.I! Figure 3.0 - Circuit Part III.I in Quartus Before importing this circuit, we will simulate a waveform to ensure that the inputs, and outputs match what we predicted in our truth table. In other words, ensure that the circuit is proper and correct before continuing further. Figure 3.1 - Functional Simulation 5

Figure 3.2 - Timing Simulation After analyzing the above simulations (Fig 3.1 and 3.2), we observe that both the timing and functional simulations are identical. We utilize the functional simulation to ensure that the circuit creates the desired outputs with the given inputs whereas the timing simulation is used to ensure that the circuit is working at the correct speed. For fun, we ran the timing simulation and oddly enough we should expect a few ms delay in the timing simulation in a real-life application. However, this was unfortunately not shown here. Nevertheless, the above waveforms prove to be correct as we can compare our theoretical truth table (as seen below) to the output of S and Cout, which match, proving that our circuit on Quartus is identical to the one we gave in the pre-lab. This proves that our circuit is correct and we are ready to be uploaded onto the FPGA board. Secondly, we opted to also create the circuit in Part III.II as seen in Figure 3.3. 6

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Figure 3.3 - Circuit Part III.II in Quartus This circuit is slightly different from the previous one, although it shares the same roots as the circuit seen in Figure 1.1 or 3.0, it contains two block diagrams, “test_counter” & “seven_segs”. These block diagrams allowed the circuit when uploaded to the FPGA to run by itself, increasing its value up to 8 and then restarting at 0 and counting up again. Additionally, this circuit displayed its outputs not only on the two LEDs we were analyzing beforehand but as well as one of the seven segment displays! This last change makes it much easier to understand what the circuit is doing from a human perspective. Discussion and Conclusions In conclusion, this lab demonstrated the abilities of the full adder as a circuit, demonstrated how to build a full adder, how to use and understand waveforms as well as truth tables etc… We briefly looked at more advanced methods of input/output while still using the same circuit and saw some very interesting results. All in all this lab was quite enjoyable, the circuit was easy to understand and its behavior made it exciting to do this lab. A problem that I encountered was with regard to the pre-lab. I believed that Part I and Part II were to be done at home on our own machine. However, I don’t quite understand how I was supposed to transfer my Quartus design file on my PC to the university’s PC… I ended up having to remake the circuit on the PC in the laboratory. For this lab, this was not a major setback, however, I am concerned that it could escalate to that in future, more complicated labs. 7