EE342Lab-10Fall2022

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EE 342 – Electronics Laboratory (Fall 2022) Lab – 10 (November 8 & 10, 2022) MOSFET voltage divider biasing and evaluation of Common-Gate (CG) amplifier. Lab Report for Lab-10: Due on November 15 (Tuesday Session), November 17 (Thursday Session), 2022 Objectives: • Analyze voltage divider biasing circuit for the MOSFET • Measure Gain in low frequency, high frequency and mid-band region of CG Amplifier • Plot Frequency response of CG amplifier • Measure the input and output impedance of CG amplifier • Simulate CG Amplifier with SPICE • Compare the calculated, measured, and simulated performance parameters of the CG amplifier, and explain with reasons the percentage difference between the calculated, measured, and simulated values • Write the conclusion with discussion of the results Reference: Chapter- 5&7 of the Textbook “Microelectronic Circuits” by Sedra, Smith, Crusone, Gaudet (Eighth Edition) Oxford University Press Background Theory: Following Figure-1 from Chapter-7 of the text book shows CG amplifier biased with current source I . Figure -1: Common – Gate (CG) Amplifier

Overall Voltage Gain 𝐺𝐺 𝑣𝑣 = � 𝑅𝑅 𝑖𝑖𝑖𝑖 𝑅𝑅 𝑖𝑖𝑖𝑖 + 𝑅𝑅 𝑠𝑠𝑖𝑖𝑠𝑠 � � 𝑠𝑠 𝑚𝑚 � 𝑅𝑅 𝐷𝐷 ││𝑅𝑅 𝐿𝐿 �� Output resistance R o = R D , R in = [1/ g m ] Equipment: Oscilloscope, function generator, DMM, CD4007 chips, resistances, capacitances. Use measured values of resistances and capacitances. Obtain data sheet for the CD4007 from the internet. Procedure: 1. The chip CD4007 contains six MOSFET, i.e. 3 n-channel and 3 p-channel MOSFETs connected as shown in Figure-2. The digit by each terminal indicates the pin number on the 14-pin DIP package. Note that pin 14 (V DD ) must always be connected to the most positive power supply voltage, and pin 7 (V SS ) must always be connected to the most negative (or ground) power supply voltage in order to keep body-source and body-drain junction from becoming forward biased. This is what provides electrical isolation between the different MOSFETs in the integrated circuit, and if this isolation fails, all of the MOSFETs end up being shorted together with completely unpredictable results. Although it is not shown in the schematic, each of the three inputs to the MOSFET gates (pins 3, 6, & 10) have two electrostatic discharge (ESD) protection diodes that connect them to the VDD and VSS power rails. For enhancement mode n-MOSFET the gate to source voltage must be positive, and no drain current will flow until V GS exceeds the positive threshold voltage V t . The MOSFET can be easily damaged by static electricity, be careful in handling the MOSFET.

Figure-2: Pin connections of CD4007 2. Set up circuit for voltage divider biasing shown in Figure-3, and measure I D = I S , V GS, V S , V D , and V DS . Compare with the calculated values of I D , V GS, V S , V D , and V DS by finding percentage difference between measured and calculated values. What are the sources of difference between the measured and calculated values? Use the n-MOSFET parameters measured in Lab-5, i.e. V t , r o , g m , V A , K n , and remember g m value depends on operating point Q-point. Remember there is no single correct value for Q-point; it will be different depending on the value of R S , R D and power supply V DD . Figure – 3: Use V DD = 10V, R G1 = 1MΩ R G2 = 100K Ω , R D = 220Ω, R S = 100Ω 3. Using the voltage divider biasing in step-2 set up the circuit for a common gate amplifier shown in Figure-4. Apply an input v sig ~ 10 mV peak signal at 5 KHz, measure the output peak value v o across load resistance 5 KΩ. Find the voltage gain of the amplifier A v = (v o /v sig ). 4. Draw small signal equivalent circuit of Figure-4 and calculate the voltage gain expression. Compare the calculated voltage gain A v with the measured voltage gain in step-3 by finding the percentage difference. Figure – 4: CG Amplifier circuit using V DD = 15V, R G1 = 1MΩ R G2 = 1M Ω, R D = 2K Ω, R L = 10KΩ, R S = 2K Ω, C C1 =100µF, C C2 = 10µF, C G = 10µF, R sig = 50Ω, and an n-MOSFET from CD4007 5. Apply an input v sig~ 10 mV peak signal at 500Hz, measure the output peak value v o across load resistance 5 KΩ. Increase the frequency of the input signal while keeping amplitude the same by step of 1KHz and find output at each increment of frequency. Present the data in a table showing input signal amplitude, frequency of input signal, output voltage v o amplitude, and gain A v = (v o /v sig ). Increase the frequency till the output voltage drops below 0.707v o of the mid-band value, i.e. mid-band is the range of frequencies when output voltage or gain remains the same.

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6. Plot the voltage gain A v = (v o /v sig ) vs. the frequency (f). Find the band-width of amplifier (BW) which is the difference between upper cutoff frequency f H and lower cutoff frequency f L , i.e. BW=(f H - f L ) 7. Measure input resistance R in = [v in /i in ] = [[(1/g m )] and output resistance R out = [(v oc – v load )/i out ] = [R D ] where v oc is the output voltage without Load resistance R load and v load is the output voltage with load resistance R load . 8. Find current gain A i = [i out /i in ] = [R D /(R D + R L ) ] 9. Change load resistance R load with 100Ω and 30KΩ, and measure maximum ou tput voltage swing and voltage gain without output clipping in the mid-band. Comment on the loading effect. 10. By increasing input signal amplitude in mid-band, find the maximum value of undistorted peak- peak output voltage. 11. Simulate the common drain amplifier with PSPICE for DC and AC analysis, and use probe command to plot frequency response of the CG amplifier. 12. Compare the measured and calculated values. Find percentage difference, and explain with reasons the sources contributing to difference in values of calculated and simulated values with reference to measured values. 13. The data in all of the above steps must be presented in tables, and in graphical form. The conclusions should be describing the measured values with reference to sources of error and should cross reference the figures when explaining the results. Lab Report for Lab-10: Due on November 15 (Tuesday Session), November 17 (Thursday Session), 2022 Lab Report: Lab report is due at the start of the next lab, however, check with Teaching Assistant when a report is due. The report should include all data in tabulated form, plot of the data, recorded waveforms, with conclusion discussing the result. Students must follow the guidelines for submitting and writing of the Lab. reports. The students are required to record all data taken during Lab. in the notebook/Laptop and get the signature of Teaching Assistant or show him/her on Laptop at the conclusion of the Lab. A record of the completion of the Lab. will be maintained by Teaching Assistant for assigning points towards final grade for the Lab. notebook. SPICE Model for n-MOSFET on CD4007 Chip: The MOSFET spice model includes the parameter PHI, which is the "surface potential" for the device. It is equivalent to the 2*phi. The MOSFET threshold is determined for spice level-1 models by V_thresh = VTO + GAMMA*( sqrt(PHI+V_sb) - sqrt(PHI) ) .model CD4007 NMOS + Level=1 Gamma= 2.7 Xj=0 + Tox=1200n Phi=.6 Rs=0 Kp=111u Vto=2.0 Lambda=0.01 + Rd=0 Cbd=2.0p Cbs=2.0p Pb=.8 Cgso=0.1p + Cgdo=0.1p Is=16.64p N=1 L=10E-6 W=30E-6 * L & W added 2/22/07 -DMH .model CD4007 PMOS

+ Level=1 Gamma= 2.7 Xj=0 + Tox=1200n Phi=.6 Rs=0 Kp=55u Vto=-1.5 Lambda=0.04 + Rd=0 Cbd=4.0p Cbs=4.0p Pb=.8 Cgso=0.2p + Cgdo=0.2p Is=16.64p N=1 L=10E-6 W=60 Low and high frequency cutoff values (3dB) taken from Chapter-10 f L = highest value of the f p1 and fp2 CG Amplifier 𝑅𝑅 𝑖𝑖𝑖𝑖 = 𝑟𝑟 0 + 𝑅𝑅 𝐿𝐿 1 + 𝑠𝑠 𝑚𝑚 𝑟𝑟 0 𝑅𝑅 𝑔𝑔𝑔𝑔 = 𝑅𝑅 𝐿𝐿 ││𝑅𝑅 0 𝑅𝑅 𝑔𝑔𝑔𝑔 = 𝑅𝑅 𝑔𝑔 | │𝑅𝑅 𝑖𝑖𝑖𝑖 𝑅𝑅 0 = 𝑟𝑟 0 + 𝑅𝑅 𝑔𝑔𝑖𝑖𝑔𝑔 + �𝑠𝑠 𝑚𝑚 𝑟𝑟 0 𝑅𝑅 𝑔𝑔𝑖𝑖𝑔𝑔 � 𝑓𝑓 𝑃𝑃 1 = 1 2 𝛱𝛱𝐶𝐶 𝐶𝐶𝐶𝐶 �𝑅𝑅 𝑔𝑔 𝑖𝑖 𝑔𝑔 + 𝑅𝑅 𝑔𝑔 1 𝑠𝑠 𝑚𝑚 � 𝑓𝑓 𝑃𝑃2 = 1 2 𝜋𝜋𝐶𝐶 𝐶𝐶2 ( 𝑅𝑅 𝐷𝐷 + 𝑅𝑅 𝐿𝐿 ) 𝑓𝑓 𝐻𝐻 = 1 2𝜋𝜋�𝐶𝐶 𝑔𝑔𝑔𝑔 𝑅𝑅 𝑔𝑔𝑔𝑔 +�𝐶𝐶 𝑔𝑔𝑔𝑔 +𝐶𝐶 𝐿𝐿 �𝑅𝑅 𝑔𝑔𝑔𝑔 � Or 𝑓𝑓 𝐻𝐻 = 1 2 𝜋𝜋𝑐𝑐 𝑔𝑔𝑔𝑔 𝑅𝑅 𝐿𝐿

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