LAB3EEE64

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American River College *

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Electrical Engineering

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Apr 28, 2024

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Uploaded by DukeKnowledge9301

Cover Page: - Caudill, William - CSC/EEE 64 LAB Section 9 -Professor Wekanda, S.

1. Lab Objectives and Goals: 1.1 The primary objectives of this lab are to: - Design and test simple logic gates using Verilog & Quartus. - Design an XOR circuit (with NAND gates) using Verilog & Quartus. - Derive the equation of a system function using K-maps. - Design a Combinational circuit in MultiSim, from the K-map equation. - Design a Combinational circuit from K-map equation using Verilog & Quartus. - Design a Test-bench in Verilog to test Verilog designs. 1.2 Goals: My goal is to learn how to implement circuit design, eventually completing it in Multisim and verifying the results in Verilog HDL and waveform. 2. Lab Preparations and Challenges: To prepare for this lab, I attended lectures where we learned about K-Maps. This method was instrumental in preparing for this lab as it helped us minimize logical expressions, saving us in our design. However, a significant challenge was the minimal training on Verilog. I was not able to complete this lab on time and had to spend many hours learning Verilog code. I now understand the difference between dataflow and structural design, which are both helpful in certain cases. 2.1 Outline of lab In Lab 3 Part 1, I learned how to use Verilog and design an XOR circuit. I coded the function using Verilog/FPGA, created a test bench for the Verilog code, and compiled it. I simulated the code and obtained the results in a waveform using Multisim. I found the equation for the system function using K-maps, designed the function with Multisim, simulated and recorded the results. I used all input combinations & a table to compare my expected “f” results with Multisim results and demoed my solutions to the instructor. In Lab 3 Part 2, I reviewed logic gates & XOR Verilog Design examples. I used the Quartus tutorial provided to simulate the Verilog design of each of the gates and checked if results are comparable to each gate's Truth table. I reviewed the XOR circuit and corresponding example of Verilog code (Structural & Data flow). I used the Quartus tutorial provided to simulate the XOR Verilog design codes and compared the Waveform/Multisim results with XOR expected results.

In Lab 3 Part 3, I drew the logic diagram (with internal and external signals) for my final reduced equation/circuit using standard AND OR NOT symbols. I wrote the Verilog description using “Structural Modeling”, compiled, and tested my design against the truth table. In Lab 3 Part 4, I found the final equations for both F1 and F2, showing all the work (K-maps, Boolean Algebra, DeMorgan’s). I implemented the circuit in Multisim and Verilog (with F1 & F2 in the same circuit), using the four (or less) integrated circuits (ICs). I compared Multisim and Verilog results. 3. Results: The lab required deriving two equations for an XOR gate using NAND gates and using only NOT, AND, OR gates by minimizing the function. The truth tables for F1 corresponded to the Boolean expression: A&~B&~C|~C&D&B|~C&D&~A. EQ. 1 The truth table for F2 corresponds to the Boolean expression: ~C&D|C&~B|C&~D|~A&~B. EQ.2 3.1 Images of Demonstrations:

Figure 1Testbench for the XOR gates in fig.2,fig.3 Figure 2 XOR gate implemented id Verilog using NAND gates Figure 3: Waveform of the NAND gate shown in fig.2

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