LAB3EEE64

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American River College *

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Electrical Engineering

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Apr 28, 2024

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Cover Page: - Caudill, William - CSC/EEE 64 LAB Section 9 -Professor Wekanda, S.

1. Lab Objectives and Goals: 1.1 The primary objectives of this lab are to: - Design and test simple logic gates using Verilog & Quartus. - Design an XOR circuit (with NAND gates) using Verilog & Quartus. - Derive the equation of a system function using K-maps. - Design a Combinational circuit in MultiSim, from the K-map equation. - Design a Combinational circuit from K-map equation using Verilog & Quartus. - Design a Test-bench in Verilog to test Verilog designs. 1.2 Goals: My goal is to learn how to implement circuit design, eventually completing it in Multisim and verifying the results in Verilog HDL and waveform. 2. Lab Preparations and Challenges: To prepare for this lab, I attended lectures where we learned about K-Maps. This method was instrumental in preparing for this lab as it helped us minimize logical expressions, saving us in our design. However, a significant challenge was the minimal training on Verilog. I was not able to complete this lab on time and had to spend many hours learning Verilog code. I now understand the difference between dataflow and structural design, which are both helpful in certain cases. 2.1 Outline of lab In Lab 3 Part 1, I learned how to use Verilog and design an XOR circuit. I coded the function using Verilog/FPGA, created a test bench for the Verilog code, and compiled it. I simulated the code and obtained the results in a waveform using Multisim. I found the equation for the system function using K-maps, designed the function with Multisim, simulated and recorded the results. I used all input combinations & a table to compare my expected “f” results with Multisim results and demoed my solutions to the instructor. In Lab 3 Part 2, I reviewed logic gates & XOR Verilog Design examples. I used the Quartus tutorial provided to simulate the Verilog design of each of the gates and checked if results are comparable to each gate's Truth table. I reviewed the XOR circuit and corresponding example of Verilog code (Structural & Data flow). I used the Quartus tutorial provided to simulate the XOR Verilog design codes and compared the Waveform/Multisim results with XOR expected results.

In Lab 3 Part 3, I drew the logic diagram (with internal and external signals) for my final reduced equation/circuit using standard AND OR NOT symbols. I wrote the Verilog description using “Structural Modeling”, compiled, and tested my design against the truth table. In Lab 3 Part 4, I found the final equations for both F1 and F2, showing all the work (K-maps, Boolean Algebra, DeMorgan’s). I implemented the circuit in Multisim and Verilog (with F1 & F2 in the same circuit), using the four (or less) integrated circuits (ICs). I compared Multisim and Verilog results. 3. Results: The lab required deriving two equations for an XOR gate using NAND gates and using only NOT, AND, OR gates by minimizing the function. The truth tables for F1 corresponded to the Boolean expression: A&~B&~C|~C&D&B|~C&D&~A. EQ. 1 The truth table for F2 corresponds to the Boolean expression: ~C&D|C&~B|C&~D|~A&~B. EQ.2 3.1 Images of Demonstrations:

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Figure 1Testbench for the XOR gates in fig.2,fig.3 Figure 2 XOR gate implemented id Verilog using NAND gates Figure 3: Waveform of the NAND gate shown in fig.2

Figure 4 Verilog code for XOR gate using a package of only AND,OR,NOT gates. Figure 5 The waveform for Verilog code in fig.4 XOR created from NAND fig.2,fig3 Result XOR expected results Result XOR created from AND,OR,NOT fig.4, fig.5 0 0 0 0 0 0 0 1 0 1 1 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 0 1 Table 1Results for XOR gate created in figures 1-6. Compared here

Figure 6 Hand Calculations of minimization using K-maps for F1 and De’Morgans law for F2. Figure 7 This is the Multisim creation of the two equations in fig. 6 above.

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Figure 8 Testbench for F1 and F2 Figure 9 Design in Verilog for the minimize equations. This is made to verify the results that we found in fig. 7 Figure 10 Here is the Waveform for fig.9. As we can see the results verify.

Input F1 (figure 10.) F2 (figure 10.) F1(Assigned) F2(Assigned) 0 0 0 0 0 1 0 1 0 0 0 1 1 1 1 1 0 0 1 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 1 1 0 0 1 0 1 0 1 1 1 0 0 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 1 1 1 1 0 1 0 0 1 0 1 1 0 1 1 0 1 0 1 1 1 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 1 0 0 1 0 1 1 1 1 1 0 0 0 0 Table 2 Compared results from figure 10, against the assigned values from the professor. 5. Conclusion: This lab was a comprehensive exercise in using Verilog to design logic circuits, simulating them using Multisim, and comparing the results with expected outcomes. I also gained experience in using K-maps to derive equations for system functions and implementing the circuits in Multisim. The challenges I faced included the limited training on Verilog, but with dedicated effort, I was able to overcome them and successfully complete the lab. 5.1 Key Takeaways about application: The steps of implementing a circuit and comparing results in Verilog: 1. Design the Circuit: First, you need to design the circuit using Multisim. This involves selecting the appropriate components from the component library and connecting them together to form the desired circuit. You can use standard logic gates, flip-flops, and other components available in Multisim to build your circuit. 2. Configure Inputs and Outputs: Once the circuit is designed, you need to configure the inputs and outputs. Assign appropriate voltage levels or logic states to the input signals of the circuit. Similarly, define the output signals that you want to observe and analyze. 3. Simulate the Circuit: After configuring the inputs and outputs, you can simulate the circuit in Multisim. This simulation will provide you with the expected results based on the circuit design and the input values. You can run the simulation and observe the behavior of the circuit, including the waveforms and logic states of the signals.

4. Obtain the Results: Once the simulation is complete, you can obtain the results from Multisim. These results include the waveforms, logic states, and any other relevant data that you configured to be displayed. You can analyze these results to verify the correctness of your circuit design. 5. Implement the Circuit in Verilog: After obtaining the results from Multisim, you need to implement the same circuit in Verilog. This involves writing the Verilog code that represents the circuit's behavior and structure. You can use structural modeling or dataflow modeling techniques to describe the circuit in Verilog. 6. Simulate the Verilog Code: Once the Verilog code is written, you can simulate it using a Verilog simulator such as Multisim. This simulation will provide you with the expected results based on the Verilog code and the input values. You can run the simulation and observe the waveforms and logic states of the signals. 7. Compare the Results: Finally, you can compare the results obtained from Multisim with the results obtained from the Verilog simulation. Compare the waveforms, logic states, and any other relevant data to ensure that they match. Any discrepancies between the results may indicate errors in either the Multisim circuit or the Verilog code. By comparing the results from Multisim and Verilog, you can validate the correctness of your circuit design and the accuracy of your Verilog implementation. This comparison helps ensure that the circuit behaves as expected and that the Verilog code accurately represents the circuit's behavior.

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