Exam_Note_Sheet_CSE230

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Arizona State University *

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230

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Computer Science

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Dec 6, 2023

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Compilation Process: Backend - Arranges the symbol table in memory and generates final executable machine code. Parts of the Compilation Process - Lexical Analysis, Syntax Analysis, Optimization, Linking, Code Generation Middle Stage - Performs program analysis and optimization. Lexical Analysis - Separates the input source code text into tokens. Syntax Analysis - Performs syntax rules checking and constructs a symbol table and abstract syntax tree. Computer Architecture: Data Path - Module where registers belong. Registers - Store temporary results of calculations. ALU (Arithmetic Logic Unit) - Part of the Data Path module. Bus - Carries data between the ALU, registers, memory, and peripherals. IO / Peripherals - Acts as an interface between the processor and the outside world, including long-term storage and user interfaces. Architecture - Computers having the same machine language indicates they share the same architecture. CPU Components: Instruction Cycle - Fetch, decode, execute, store. Control Unit - Coordinates the flow of information around the processor. Fetch Stage - Involves the Program Counter and Instruction Memory. Execute Stage - ALU is active during this stage. Store Stage - Data Memory and Program Counter are active. Clock and Performance: Clock Frequency - Defined as f = 1/T (1Hz = 1 cycle per second). Pareto Principle - 80% of results generated by 20% of code. Improving Performance - Decreasing clock cycles used by the program or decreasing CPI can improve performance. Number Systems and Representation: Binary System - Uses 2 symbols. Decimal System - Uses 10 symbols. Binary Representation - "0" represented by low voltage, "1" by high voltage. Two's Complement - Negative numbers indicated by the most significant bit as 1. Exceptions and Arithmetic Operations: Overflow - Occurs when adding to a variable at the upper end of the datatype range. Underflow - Occurs when subtracting from a variable at the lower end of the datatype range. Endianness and Data Representation: Big-Endian - Most significant byte stored at a lower address. Little-Endian - Least significant byte stored at a lower address. Endianness Issue - When transferring memory blocks between processors with different endianness. Procedure Calls and MIPS Registers: MIPS Registers - $v0 for return value, $t0 for temporary values, $a0 for parameter values, $ra for return address.

Pipelining and Processor Design: Pipelining - Increases performance but increases processor design complexity. Pipeline Registers - Store control signals, execution results, and necessary instruction data. Speedup in Pipelined Design - Theoretical maximum speedup of N stages over single cycle design is N. Hazards in Pipelining: Hazard Types - Structure, Control, and Data Hazards. Handling Hazards - Forwarding and Stall techniques used to reduce their impact. Branch Prediction: Static Branch Prediction - Offers a simple implementation advantage. 2-bit History Table Branch Prediction - Utilizes a history table storing multiple bits, mapping the branch instruction address to indicate the branch behavior. A state machine updates the table. Dynamic Branch Prediction Disadvantage - Increases hardware complexity. Dynamic Branch Prediction Advantages - Increased performance. High branch prediction accuracy (better than chance). 1-bit History Table Branch Prediction - Uses a history table with a single bit mapped to the branch instruction address, indicating the previous branch state. Static Branch Prediction - Hardware specifies to always predict a taken or untaken branch. Memory Hierarchy: Memory Close to CPU - SRAM is placed closer to the CPU in the memory hierarchy. Slowest Memory Type - Disk memory is generally the slowest. Memory for Intermediate Results - SRAM is used for intermediate calculation results. Large-scale Long-Term Storage - Implemented with disk memory technology. Internet Router Settings Storage - Flash memory should be used to save settings. Volatile Memory Types - DRAM and SRAM are volatile. Most Expensive Memory Type - SRAM is the most expensive. Caches and Registers - Implemented with SRAM technology. Cache Locality: L1 Cache Focus - Supports temporal locality. Array Element Access - Pre-loading other data in the array demonstrates spatial locality. Instructions Pre-loading into Cache - Shows spatial locality. Loop Instructions in Cache - An example of temporal locality. Level-2 Cache Focus - Aimed at low miss rates. Memory Design and Architecture: Memory Locality Types - Spatial and temporal locality are used in memory design. Variable Access in Cache - An example of temporal locality. Level-2 Cache Focus - Concentrates on supporting spatial locality. SIMD Architecture Examples - Basic Graphics Processing Unit (GPU). SISD Architecture - Executes one instruction on one set of data at a time. MIMD Architecture - Executes multiple instructions on different sets of data at a time. MIMD Architecture Examples - Intel Xeon Processor. SISD Architecture Examples - Intel Pentium Processor. CPU Design and Multiprocessing - Adopted multiprocessing architectures to manage heat dissipation and handle complex problem-solving demands.

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