HW7csc 137-25AryaAswini

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California State University, Sacramento *

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137

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Computer Science

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Dec 6, 2023

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Arya Aswini HW#7 CSc 137 (25 points) P1. In order to minimize the duration of a read cycle, the _oe can be asserted at any time within a maximum time after the _ce is asserted, as illustrated in the timing diagram. (5 pts) A. True B. False
P2. A memory write cycle is similar to a read cycle, except that data must be placed on the data bus at the same time that _ce is asserted or within a maximum delay after _we is asserted to minimize the time the data bus is used. Figure 7.17 illustrates an SRAM memory write cycle. (5 pts) I. A memory cycle is initiated by which component in the computer motherboard? The CPU (Central Processing Unit) is the part of the computer motherboard that starts the memory cycle. II. A memory cycle, typically, how many CPU clock cycles to complete? It takes about 2 clock cycles, the first for placing the data over the data bus and the second for sending the data over the data bus.
7.10 Consider a 32-bit data bus SDRAM. Given that the clock frequency of the bus is 200MHz, what is the peak memory bandwidth in megabyte per second (MBs)? (5 pts) 7.11 Consider a 64-bit data bus SDRAM. Given that the clock frequency of the bus is 200MHz, what is the peak memory bandwidth in megabyte per second (MBs)? (5 pts)
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7.12 Consider a 32-bit data bus DDR SDRAM. Given that the clock frequency of the bus is 200MHz, what is the peak memory bandwidth in megabyte per second (MBs)? (5 pts)

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