Completed-C310-HW4

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Name:____ CMIS 310 HOMEWORK #4 – Week #4 This homework is worth 10% of your course grade. Read each problem carefully. Failure to follow the instructions for a problem will result in a zero score for that problem. Submit the completed Homework via Assignment in LEO. 1. Do Exercise 2 in Chapter 5 (A Closer Look at Instruction Set Architectures) of Null and Lobur 2. Show how the following values would be stored by byte-addressable machines with 32-bit words, using little endian and then big endian format. Assume that each value starts at address 10 16 . Draw a diagram of memory for each, placing the appropriate values in the correct (and labeled) memory locations. a. 0x456789A1 456789A1 16 Big Endian Value 45 67 89 A1 Address X X+1 X+2 X+3 Little Endian Value A1 89 67 45 Address X X+1 X+2 X+3 b. 0x0000058A 0000058A 16 Big Endian Value 00 00 05 8A Address X X+1 X+2 X+3 1

Little Endian Value 8A 05 00 00 Address X X+1 X+2 X+3 c. 0x14148888 14148888 16 Big Endian Value 14 14 88 88 Address X X+1 X+2 X+3 Little Endian Value 88 88 14 14 Address X X+1 X+2 X+3 2. Do Exercise 12 in Chapter 5 (A Closer Look at Instruction Set Architectures) of Null and Lobur 12. Convert the following expressions from infix to reverse Polish (postfix) notation. a) X × Y + W× Z + V × U Answers a) X Y × W Z × V U × + + Converted: X Y × W Z × + V U × + Answer: X Y × W Z × + V U × + b) W × X + W 3 (U × V + Z ) Converted: W X × W 3 U V × Z + × + Answer: W X × W 3 U V × Z + × + 2

c) (W × (X + Y × (U × V )))/(U × (X + Y )) Converted: W X Y U V × × + × U X Y + × / Answer: W X Y U V × × + × U X Y + × / 3. Do Exercise 14 in Chapter 5 (A Closer Look at Instruction Set Architectures)of Null and Lobur 14. Convert the following expressions from reverse Polish notation to infix notation. a. W X Y Z - + × W * (X + Y – Z) b. U V W X Y Z + × + × + U + V * (W + X * (Y + Z)) c. X Y Z+V W - × Z + + (X + (((Y + Z) * (V - W)) + Z)) 4. Do Exercise 22 in Chapter 5 (A Closer Look at Instruction Set Architectures) of Null and Lobur 22. Suppose we have the instruction Load 500. Given that memory and register R1 contain the values below: and assuming that R1 is implied in the indexed addressing mode, determine the actual value loaded into the accumulator and fill in the table below: 3

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Mode Value Loaded into AC Immediate 500 Direct 100 Indirect 600 Indexed 800 5. Do Exercise 28 in Chapter 5 (A Closer Look at Instruction Set Architectures)of Null and Lobur 28. The memory unit of a computer has 256K words of 32 bits each. The computer has an instruction format with four fields: an opcode field; a mode field to specify one of seven addressing modes; a register address field to specify one of 60 registers; and a memory address field. Assume an instruction is 32 bits long. Answer the following: a. How large must the mode field be? 3 bits b. How large must the register field be? 6 bits c. How large must the address field be? 18 its d. How large is the opcode field? 7 bits 4

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