You have a 2-way set associative, write-back cache with 64 bytes in each cache line. Write back is handled by hardware and does not involve any delays. Memory latency is 30 cycles, bandwidth is 8 bytes per cycle. You can choose between: A. 256KB cache with access cost of 1 cycle to read a word into a register, and a miss rate of 15% o B. 1MB cache with a miss rate of 5% but aaccess cost of 2 cycles for every transfer between a register and cache. For each configuration of cache, calculate: size of tag for a cache line, and size of cache addresses (both sizes in number of bits).

You have a 2-way set associative, write-back cache with 64 bytes in each cache line. Write back is handled by hardware and does not involve any delays. Memory latency is 30 cycles, bandwidth is 8 bytes per cycle. You can choose between: A. 256KB cache with access cost of 1 cycle to read a word into a register, and a miss rate of 15% o B. 1MB cache with a miss rate of 5% but aaccess cost of 2 cycles for every transfer between a register and cache. For each configuration of cache, calculate: size of tag for a cache line, and size of cache addresses (both sizes in number of bits).

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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