V,(s) (i) Derive the transfer function, G(s)= V,(s)* (ii) Design the combination of resistor, R2, and capacitor, C, that can produce the step response with an overshoot of 10% and a settling time 1.5 ms. (iii) The capacitor is completely discharged before the step input voltage (V;) of 10 volts is supplied to the system. Formulate the output function of Vo in the time domain. (iv) Plot the unit step response of Vo(t) in a graph (t from 0 s to 3 ms). Indicate the settling time, peak time, and maximum overshoot in the graph.

V,(s) (i) Derive the transfer function, G(s)= V,(s)* (ii) Design the combination of resistor, R2, and capacitor, C, that can produce the step response with an overshoot of 10% and a settling time 1.5 ms. (iii) The capacitor is completely discharged before the step input voltage (V;) of 10 volts is supplied to the system. Formulate the output function of Vo in the time domain. (iv) Plot the unit step response of Vo(t) in a graph (t from 0 s to 3 ms). Indicate the settling time, peak time, and maximum overshoot in the graph.

Introductory Circuit Analysis (13th Edition)

13th Edition

ISBN:9780133923605

Author:Robert L. Boylestad

Publisher:Robert L. Boylestad

Chapter1: Introduction

Section: Chapter Questions

Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...

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Question

Fig. Q2(b) illustrates the electrical network with passive components. The Vi
and Vo are the input and output voltage, respectively

V,(s)
(i)
Derive the transfer function, G(s) =
V,(s)
(ii)
Design the combination of resistor, R2, and capacitor, C, that can
produce the step response with an overshoot of 10% and a settling time
1.5 ms.
(iii)
The capacitor is completely discharged before the step input voltage (V:)
of 10 volts is supplied to the system. Formulate the output function of
Vo in the time domain.
Plot the unit step response of Vo(t) in a graph (t from 0 s to 3 ms). Indicate
the settling time, peak time, and maximum overshoot in the graph.
(iv)

Fig. Q2(b) illustrates the electrical network with passive components. The Vị
and Vo are the input and output voltage, respectively.
L = 1H
in
R2
R1
2MQ
+
Vi
C
V.
Fig. Q2(b)
+

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