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Suppose you have a RISC machine with a 2.7 GHz clock (i.e., the clock ticks 2.7 billion times per second). This particular computer uses an instruction cache, a data cache, an operand fetch unit, and an operand store unit. The instruction set includes simple instructions with the following timings: SET _reg, immed; 3 clock cycles LOAD reg, mem; 4 clock cycles ADD reg, reg ;3 clock cycles ADD reg, immed; 2 clock cycles LOOP_LabelName ; 8 clock cycles Assume that the following code fragment is used to sum the element of a numeric array. SET reg1, 0 ;initialize sum SET reg2, MAX_SIZE ;initialize loop counter

Suppose you have a RISC machine with a 2.7 GHz clock (i.e., the clock ticks 2.7 billion times per second). This particular computer uses an instruction cache, a data cache, an operand fetch unit, and an operand store unit. The instruction set includes simple instructions with the following timings: SET _reg, immed; 3 clock cycles LOAD reg, mem; 4 clock cycles ADD reg, reg ;3 clock cycles ADD reg, immed; 2 clock cycles LOOP_LabelName ; 8 clock cycles Assume that the following code fragment is used to sum the element of a numeric array. SET reg1, 0 ;initialize sum SET reg2, MAX_SIZE ;initialize loop counter

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Suppose you have a RISC machine with a 2.7 GHz clock (i.e., the clock ticks 2.7 billion times per second). This particular computer uses an instruction cache, a data cache, an operand fetch unit, and an operand store unit. The instruction set includes simple instructions with the following timings: SET reg, immed; 3 clock cycles LOAD reg, mem ; 4 clock cycles ADD reg, reg ; 3 clock cycles ADD reg, immed; 2 clock cycles LOOP LabelName ; 8 clock cycles Assume that the following code fragment is used to sum the element of a numeric array. SET reg1, 0 ;initialize sum SET reg2, MAX_SIZE ;initialize loop counter SET reg3, @list ;initialize array pointer ProcessArray: LOAD reg4, [reg3] ;fetch current list element ADD reg1, reg4 ;add current list element ADD reg3, 4 ;move array pointer to next element LOOP ProcessArray ;auto-decrement reg2, jump to more if reg2 # 0 If the initialization code has already executed (i.e. the SET instructions have already finished execution) how many array elements can be processed in 4.4 milliseconds (ms)? Round your answer to the nearest integer. Recall that 1 ms = 0.001 seconds. Also assume that there are no physical memory limitations, implying that the array can be as large as desired.
Transcribed Image Text:Suppose you have a RISC machine with a 2.7 GHz clock (i.e., the clock ticks 2.7 billion times per second). This particular computer uses an instruction cache, a data cache, an operand fetch unit, and an operand store unit. The instruction set includes simple instructions with the following timings: SET reg, immed; 3 clock cycles LOAD reg, mem ; 4 clock cycles ADD reg, reg ; 3 clock cycles ADD reg, immed; 2 clock cycles LOOP LabelName ; 8 clock cycles Assume that the following code fragment is used to sum the element of a numeric array. SET reg1, 0 ;initialize sum SET reg2, MAX_SIZE ;initialize loop counter SET reg3, @list ;initialize array pointer ProcessArray: LOAD reg4, [reg3] ;fetch current list element ADD reg1, reg4 ;add current list element ADD reg3, 4 ;move array pointer to next element LOOP ProcessArray ;auto-decrement reg2, jump to more if reg2 # 0 If the initialization code has already executed (i.e. the SET instructions have already finished execution) how many array elements can be processed in 4.4 milliseconds (ms)? Round your answer to the nearest integer. Recall that 1 ms = 0.001 seconds. Also assume that there are no physical memory limitations, implying that the array can be as large as desired.
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