QUESTION: Design a synchronous binary irregular counter with the following count sequence based upon your unique 5-digit middle portion of your I.D.:                                              A→B→C→D→E→A                                    Where XX-ABCDE-Y stands as your ID. XX stands for the year (16/17/18) and Y stands for the semester (1/2/3) you got enrolled in AIUB. Both XX and Y is irrelevant in your design and is not required in any part of your design. The middle portion of your I.D is a 5 digit unique number that is different for all students. Here in this design, the ABCDE represents the unique 5 digits of your I.D. So the count sequence is based upon the middle unique portion of your I.D.

Q: Q1: state whether the following identity is (a) POS,(b) SOP,) canonica POS,(d) canonical SOP…

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Q: Q3: Perform the following operation 1- (ABC 16 + A BC 16 ) 2- (33 )10 = ( ? )2 3- XNOR gate ( ? )

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A:

Q: Implement the given function with the help of de-multiplexer F(A,B,C)=£m(0,2,4,6,8) 156 237

A: Implement the given function with the help of de-multiplexer F(A,B,C)=£m(0,2,4,6,8) 156 237

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A:

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A: Please upvote me/like me. Please. Please. I am providing you the correct answer below.     Here I am…

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A:

Q: please hand written

A: The solution is given below for the above given question:

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A: The answer is given in the below step

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A: Simplification

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A: Below is the SOP form using K-map and circuit using NAND gates:

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A: In step 2, I have provided  complete solution----------

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A:

Q: Please do completely.all 3 parts

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A: In step 2, I have provided  ANSWER  with brief explanation-------------

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Q: w correct else downvot

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