If the following information is given: (for Q1 & Q2) CS= 3F2Bh, DS = 59A2h, ES = 72Fah, SS=E12Ah, BX = 4F2Ch, SI= 556Bh, DI= 872Ah, PB=435Dh, IP = 3489h, SP = 792h, and Value = 12789 Q1: Find the physical address location for the following memory segment which contains the following instructions: Address 1 Address 2 Address 3 Address 4 MOV DS, [BX][SI] ADD AL, [BP+3A2Fh] MOV CX, Value[BP] MOV ES: [C23Dh], 2AFh Q2: Find the EA for each of the above instructions

If the following information is given: (for Q1 & Q2) CS= 3F2Bh, DS = 59A2h, ES = 72Fah, SS=E12Ah, BX = 4F2Ch, SI= 556Bh, DI= 872Ah, PB=435Dh, IP = 3489h, SP = 792h, and Value = 12789 Q1: Find the physical address location for the following memory segment which contains the following instructions: Address 1 Address 2 Address 3 Address 4 MOV DS, [BX][SI] ADD AL, [BP+3A2Fh] MOV CX, Value[BP] MOV ES: [C23Dh], 2AFh Q2: Find the EA for each of the above instructions

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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2. Consider the following segment table, what are the physical addresses for the following logical addresses? Segment Base Length 0 219 600 1 14 100 580 96 (a) 1, 12 (b) 3,650 (c) 4,76 2 187 3 2300 90 1327 1952
A computer uses a mapping procedure between main and cache memory. If the main memory has 128 blocks (0 - 127) and cache memory has 32 blocks (0 - 31) with four sets (set0 - set3), List the entire block addresses of the main memory used in each of the following situations: (1) The entire block addresses of the main memory that can be placed in location 15 of the cache memory. (When the computer uses Direct Mapped Cache) (2) The entire block addresses of the main memory that can be placed in set2 of the cache memory. (When the computer uses Set Associative Cache) (3) The entire block addresses of the main memory that can be placed in location 10 of the cache memory. (When the computer uses Fully Associative Cache)
Problem 0. The following table gives some of the parameters for a number of different hardware caches. Fill in the table with the values of the missing parameters. Recall that m is the number of physical address bits, C is the cache size in bytes, B is the block size in bytes, E is the associativity, i.e., lines per set, S is the number of sets, t is the number of tag bits, s is the number of set index bits, and b is the number of block offset bits. Cache m 48 32030 (b) 48 32 24 24 C B E 16384 32 16 32768 64 65536 128 512 32 1024 8 8 4 14 1 4 S b S t
Direct Mapping Example: CPU is searching an Instruction stored at RAM address 1110011010 in cache and doesn't find it. What happens then? Tag 0000000000 ?? 0000000001 ?? Block:0, (j=0) 0000000010 Instruction-1 Line1 = 1 Tag Tag 0000000011 Instruction-2 0000000100 Instruction-3 Instruction-4 Block:1, G=1) Solution: 0000000101 Line 2 (= 2) Tag 0000000110 Instruction-5 0000000111 Instruction-6 0000001100 Instruction-7 0000001101 Instruction-8 Block:2 0000001110 Data-1 (j=2) 0000001111 Data-2 Line.3 (3) 0000011100 Data-3 0000011101 Data-4 Tag 0000011110 Data-5 0000011111 Data-6 Cache Size = 64B Size of a line = 4B Total number of Lines in Cache: m 16 RAM Size = 1KB %3D 1111111100 %3D Size of a Block= 4B Total number of Blocks, M = 256 j = 0, 1, 2, ..255 (M-1) Block 255. G =255) 1111111101 1111111110 i = 0, 1, 2, ... 15 (m-1) 1111111111
Depending on an index sent by an outside device we want to be able to call one of ten subroutines in our 68000 program. For 0 sent we call Sub0, for 1 sent we call Sub1, ., for 9 sent we call Sub9. The subroutine addresses are in a table of longwords, SubAdrs. The index value is passed to our code in d0. Write the code that uses table SubAdrs to make the call to the correct subroutine using only one JSR instruction. State any other assumptions you need.
Q e
Suppose a byte-addressable computer using set associative cache has 224 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
Consider the following table that represents part of the memory of a 16-bit address space that has an addressability of 2 bytes (like LC-3): ADDRESS OxFFFF OXOCOE OXOCOD Ox0C0C OXOCOB OXOCOA 0x0C09 0x0000 CONTENTS 1111 1111 1111 1111 1111 1110 1101 1100 0001 1011 1100 0101 0110 0101 1000 0111 1100 0000 0100 0000 0011 0001 0101 0010 0000 1100 0000 1101 0000 0000 0000 0000 The table above shows the addresses in hex (base 16) and the contents at the corresponding address in binary (base 2). A.) What are the contents in hex of the memory location at following address in binary: 0000 1100 0000 1110? (Enter hex like the following example: Ox2A3F)
3.
A memory system has 4 KB byte-addressable main memory and a direct-mapped cache that consists of 8 blocks with 16 bytes per block. The following shows the main memory address format that allows us to map addresses from main memory to cache. Note: 12 bit address, 4 bit offset, 3 bit $block, and 5 bit tag Assume the cache directory shown below:
Question 4: There is an application that requires the hardware: an Intel 8031, a Program ROM of 8Kx8, a Data ROM of 4Kx8 for look-up tables, TWO Data RAMs of 8Kx8. The memory map of the design should be: Program ROM should start at address 0000μ. Then, the Data ROM should come above the Program ROM. Finally the Data RAMs must go to the top of the memory map. There should be no gaps between the memory addresses of the external ROMs or RAMS. A. Using logic gates, draw the pin connections of the design. Label your diagram fully. B. Calculate the address space of the ROMs and RAMs of your design. C. Show the design's address space on a memory map, starting with 0000μ at the bottom and FFFFH at the top.
Suppose a computer using direct mapped cache has 232 words of main memory and a cache of 1024 blocks, where each cache block contains 32 words. How many blocks of main memory are there? What is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, block, and word fields? To which cache block will the memory reference 000063FA16 map?