Lab 5_TimeProportioningControl LAB
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EET 220 Industrial Applications Professor D. Overbye
Week 3 Lab 5 “Time Proportioning Control”
By: Deandre Wheelington
ECPI University
I pledge to support the Honor System of ECPI. I will refrain from any form of academic
dishonesty or deception, such as cheating or plagiarism. I am aware that as a member
of the academic community it is my responsibility to turn in all suspected violators of the
honor code. I understand that any failure on my part to support the Honor System will
be turned over to a Judicial Review Board for determination. I will report to a Judicial
Review Board hearing if summoned.
Name Deandre Wheelington Date: 24 Nov 23
Abstract:
In this lab, we will be demonstrating how to control the average voltage/power delivered to an op-amp load using a method known as “time-proportioning”. We will also measure the duty cycle of our output Pulse Width Modulated (PWM) signal using an oscilloscope and a formula. Introduction: We will first focus on building the circuit in this lab using multisim. Once the circuit
is built, we will open up the oscilloscope window. We will run the simulation at different loads of resistance by using our adjustable potentiometer and record our
values below in a table. The values needed to be recorded are the “On time” or the time that our load was on before it started another duty cycle, the entire duty cycle time, and finally, the measured output voltage during the set potentiometer value. We will find these values in our tables using given formulas down below.
Lab 5: Time Proportioning Control
Objectives: After performing this experiment, you will be able to:
1.
Control the average voltage/power delivered to the load using Time proportioning method.
2.
Measure the duty cycle of the Pulse Width Modulated (PWM) signal.
Procedure:
1.
Construct the following circuit using multisim.
VCC
10V
R2
10kΩ
Key=A
0 %
U1
741
3
2
4
7
6
5
1
V1
5Vpk 60Hz 0° XSC1
A
B
Ext Trig
+
+
_
_
+
_
VCC
10V
Offset = 5V
Figure 1: Time proportioning circuit
2.
Set the potentiometer to 0% and Run the simulation. Observe the oscilloscope; you should be
able to see a positive DC voltage because the op-amp is saturated. Means the voltage at the non-
inverting terminal is greater than the inverting terminal.
3.
Measure the dc output voltage using the voltage probe at pin 6. Record the result in table 1
below under output voltage.
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4.
Set the potentiometer to 10%; you should be able to see the following waveform.
Figure 2: Measuring ON time of the pulse
5.
Place the cursors 1 and 2 at the beginning and ending of the pulse as shown above.
6.
Observe the value of T2-T1, which gives the ON time of the pulse. Record the result in the table
1 below under ON time (t
ON
). Potentiometer
setting
ON Time (t
ON
)
Duty cycle
Output
Voltage
0%
N/A
100%
9.12 V
10%
12.416 ms
75.578%
9.12 V
30%
9.933 ms
60.463%
9.12 V
60%
6.781 ms
41.277%
9.12 V
90%
2.674 ms
16.277%
9.12 V
100%
N/A
0%
882 mV
Table 1: Duty cycle measurement
7.
Now place the cursors such that time period (T) of the waveform can be measured as shown
below. To measure the time period cursors must be place to cover one complete cycle. This time
period will not change since the frequency of the signal stays at 60Hz.
Figure 2: Measuring time period of the waveform
8.
The measured time period (T) is 16.428 ms .
9.
Calculate the duty cycle using the formula below. Record the duty cycle in table 1 above.
% DC = t
ON
T
∗
100
10.
Record the dc output voltage using the probe under output voltage.
11.
Now, change the potentiometer setting as listed in table 1 above and repeat steps 5 through 10.
Experiment Questions:
1.
The term duty cycle refers to the amount of time a signal is ON
compared to the period of one
complete cycle.
A. off B. on
2.
The output voltage of op-amp is positive saturation, when the voltage applied to the _______
input is greater than the Inverting input.
A. inverting B. noninverting
3.
A square wave that is 20V at its high state and 0V when it is off will produce an average DC voltage of 15 V
when its duty cycle is 75%. Formula: V
OUT
= Duty Cycle * Peak voltage
A. 7.5V B. 10V C. 15V Potentiometer @ 0%
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Potentiometer @ 10%
Potentiometer @ 30%
Potentiometer @ 60%
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Potentiometer @ 90%
Potentiometer @ 100%
Conclusion: To conclude this lab, we successfully demonstrated the difference of duty cycle times depending
on how much resistance we apply to the input voltage of our operational amplifier. In adjusting
the resistance, it displayed the outcome of how much percentage we have of a whole duty cycle
and the time it can stay on. We also noticed that our output voltage was able to be maintained
at 9.2V the entire lab up until we completely inverted the voltage amount to be about 0V at the
input side with 100% resistance applied. SOURCES:
Bartelt, T. L. (2011). Industrial Automated Systems: Instrumentation and Motion Control.
Cengage Limited. https://ecpi.vitalsource.com/books/9781305474277Bartelt, T. L. (2011).
Industrial Automated Systems: Instrumentation and Motion Control. Cengage Limited.
https://ecpi.vitalsource.com/books/9781305474277