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University of Florida *

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5320

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Electrical Engineering

Date

Jan 9, 2024

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pdf

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4

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EEE 5320 Cadence Assignment Format: Report Objectives: 1. Getting used to DC/AC simulation in Cadence 2. Getting familiar with single stage amplifier operation principle 3. Introduce the concept of output swing AC Simulation Guideline For AC simulation, first you need to give the AC magnitude as the stimuli in the schematic. Find your input, for instance, ideal voltage source (idc), and set the AC magnitude to be 1V After check & save your schematic, in ADE, go to Analysis and create a new AC analysis and then run the simulation
After successfully run the simulation, go to Results -> Direct Plot -> Main Form. Leave this window open and go back to the schematic. Choose the wire (output) that you want to plot and press Esc. The AC simulation result will pop out. For Y axis unit, you can choose either V/V by selecting Magnitude as the modifier or dB by selecting dB20 (10V/V = 20dB). The expected AC simulation result of part A is shown below
Part A W/L V in R D =5K V out 2.5V 0.6V(DC)+1V(AC) Figure 1. CS Amplifier 1) With given components value, find the W & L value that set the NMOS in saturation and the AC gain of the amplifier to be or larger than 10V/V. Include screenshot of schematic under DC simulation with annotations on and the AC magnitude result. What is the DC current of this amplifier? What is the output swing of this amplifier? Explain what limits the swing, V ds or VDD? (Output swing means the maximum output range (±V sw from the output DC operating point) allowed while all transistors can be in saturation, i.e., V out_DC ± V sw make all transistors in SAT & within the supply boundary) (Hint1: you can find the DC parameters by going to Results -> Print -> DC operating point and select the NMOS. There should be a list pops out and you can find Vth / Vdsat (Veff)) 2) If the input DC value varies by ±10mV, what is the DC current and output swing under these cases?
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Part B W/L V out 2.5V V in 1V(DC)+1V(AC) R D =10K R S =2K Figure 2. CS Amplifier with source degeneration 1) With given components value, find the W & L value that set the NMOS in saturation and the AC gain of the amplifier to be or larger than 2.5V/V. Include screenshot of schematic under DC simulation with annotations on and the AC magnitude result. What is the DC current of this amplifier? What is the output swing of this amplifier? Explain what limits the swing, V ds or VDD? 2) If the input DC value varies by ±10mV, what is the DC current and output swing under these cases?