3. Practice-DataDependencies-Solution

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Practice Questions: Q1) Consider the following RISC-V assembly code: 1) ld x1,45(x2) 2) add x7,x1,x5 3) sub x8,x1,x6 4) or x9,x5,x1 5) bne x11, x7, target 6) add x10,x8,x7 7) xor x2,x3,x4 Identify each dependence; list the two instructions involved; identify which instruction is dependent; and, if there is one, name the storage location (register or memory). Solution: Inst (2) is dependent on inst (1) through x1 Inst (3) is dependent on inst (1) through x1 Inst (4) is dependent on inst (1) through x1 Inst (5) is dependent on inst (2) through x7 Inst (6) is dependent on inst (2) through x7 Inst (6) is dependent on inst (3) through x8 Q2) Indicate the data dependences in the following RISC-V code sequence: 1) add x1, x2, x3 2) lw x4, 0(x1) 3) addi x5, x1, 100 4) sw x4, 0(x5) 5) or x4,x3,x5 Solution: Inst (2) is dependent on inst (1) through x1 Inst (3) is dependent on inst (1) through x1 Inst (4) is dependent on inst (2) through x4 Inst (4) is dependent on inst (3) through x5 Inst (5) is dependent on inst (3) through x5 Q3) Please identify all data dependencies beside each instruction:

1) lw x2, 60(x1) 2) lw x1, 40(x2) 3) slt x1, x1, x2 4) sw x1, 20(x2) Solution: lw x2, 60(x1) ● No dependencies lw x1, 40(x2) ● WAR on x1 from instr 1 ● RAW on x2 from instr 1 slt x1, x1, x2 ● WAR on x1 from instr 1 ● RAW on x2 from instr 1 ● WAW on x1 from instr 2 ● RAW on x1 from instr 2 sw x1, 20(x2) ● RAW on x2 from instr 1 ● WAR on x1 from instr 1 ● RAW on x1 from instr 3 Q4) Latencies of the major functional components of the single-cycle datapath are: Memory read: 4 ns Memory write: 4 ns Register file read: 2 ns Register file write: 2 ns ALU: 3 ns The latencies of all other components of the datapath is negligible. a) Compute the maximum possible clock frequency of the single-cycle processor.

Solution: The maximum possible clock-frequency is 1/C GHz , where C is the minimum possible clock-cycle time in nanoseconds ( the latency of the slowest instruction, which is lw in this case.) Thus: Clock cycle time ( C ) = 4 +2 +3 + 4 + 2ns ( inst. mem read + reg read + ALU + data mem read + reg.write) Clock frequency = 1/15 ns = 1/15 GHz b) The clock frequency is increased by a factor of 1.15 by making the ALU faster. Compute the latency of the new ALU. Solution: Suppose the latency of the new ALU is X ns. Then the new clock cycle time is = 4+2+X+4+2 ns, then: Clock frequency new/ clock frequency old = 1.15 Then: Clock cycle time old / clock cycle time new = 1.15 15ns/ (X ns+12ns) = 1.15 X = ? ns (c) Consider a 5-stage pipeline with stages IF ID EX MEM WB built using the functional components on the opposite page. Assume that all additional components (pipeline registers, etc.) have negligible latency. Compute the maximum clock frequency on the pipelined processor(a). Solution: The maximum clock-frequency for the pipelined datapath is 1/cp where cp is the minimum possible clock-cycle time. For a pipelined processor, cp is the latency of the slowest stage, which is 4 ns in this case. Click frequency = 1/4ns =0.25GHz

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Q5) We have a RISC-V processor with register-register arithmetic instructions that have the format R1 <- R2 op R3. The stages are as follows: Instruction fetch: 150ps Decode: 100ps Execute: 200ps Write back: 50ps 1) What rate can you clock this processor? Solution: Cycle time is equal to the latency of the slowest stage : 200ps. Then; Clock freq= 1/200ps = 5 Ghz 2) You have the option to split one stage into two. Which one would you break into two? What rate can you clock the processor? Solution: Execute stage because it is the slowest stage. EX1=100ps, EX2=100ps. 150ps cycle frequency new : 6.67 Ghz

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