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EECS 168 Introduction to VLSI Design Sheldon Tan Homework 4 solution 1. For the RC circuit shown below, the required arrival times at node 1 and 2 are respectively 2 ns and 1.2 ns. (a) Compute the required arrival time at the source node 0 . (b) If we insert one buffer with C buf = 2 pF, R buf = 10 Ω , and D buf = 5 ps at node X, what is the new required arrival time at node 0 ? a) T 0 = min i (T i − D i ) = min {T 1 − D 01 , T 2 − D 02 } D 01 = R 1 (C 1 + C 2 + C 3 + C 4 + C 5 + C 6 + C 7 + C 8 ) + R 2 (C 2 + C 3 + C 4 + C 5 ) + R 3 (C 3 + C 4 + C 5 ) + R 4 (C 4 + C 5 ) + R 5 C 5 = 10 × 19 + 60 × 12 + 60 × 9 + 60 × 6 + 60 × 3 = 1990 ps D 02 = R 1 (C 1 + C 2 + C 3 + C 4 + C 5 + C 6 + C 7 + C 8 ) + R 6 (C 6 + C 7 + C 8 ) + R 7 (C 7 + C 8 ) + R 8 C 8 = 10 × 19 + 80 × 6 + 80 × 4 + 80 × 2 = 1150 ps T 1 − D 01 = 2000 − 1990 = 10 ps T 2 − D 02 = 1200 − 1150 = 50 ps T 0 = min{T 1 − D 01 , T 2 − D 02 } = min{10 ps,50 ps} = 10 𝑝𝑠 b) D 01 ′ = R 1 (C 1 + C 6 + C 7 + C 8 + C buf ) + R 2 C buf + D buf + R buf (C 2 + C 3 + C 4 + C 5 ) + R 3 (C 3 + C 4 + C 5 ) + R 4 (C 4 + C 5 ) + R 5 C 5 = 10 × 9 + 60 × 2 + 5 + 10 × 12 + 60 × 9 + 60 × 6 + 60 × 3 = 1415 ps D 02 ′ = R 1 (C 1 + C 6 + C 7 + C 8 + C buf ) + R 6 (C 6 + C 7 + C 8 ) + R 7 (C 7 + C 8 ) + R 8 C 8 = 10 × 9 + 80 × 6 + 80 × 4 + 80 × 2 = 1050 ps T 1 − D 01 ′ = 2000 − 1415 = 585 ps T 2 − D 02 ′ = 1200 − 1050 = 150 ps T 0 = min{T 1 − D 01 ′ , T 2 − D 02 ′ } = min{585 ps,150 ps} = 150 𝑝𝑠

(a) Answer: - Let's consider the possible scenarios: Inputs to Gate A (X and Y): Since Gate A's output is stuck at 1, we can't determine the actual values of X and Y based on the output. They could be anything. Inputs to Gate B (Z and W): We don't have information on a fault in Gate B, so it should function normally. The inputs Z and W will determine its output as per normal NAND operation. Gate C's Behavior: The inputs to Gate C are the outputs of Gates A and B. Since Gate A's output is stuck at 1, one of the inputs to Gate C is always 1. The other input is the output of Gate B. To detect the stuck-at-1 fault at Gate A's output, we need to consider how it affects the overall circuit output (o). Since Gate C is a NAND gate, if one of its inputs is always 1 (from Gate A), its output will depend solely on the other input (from Gate B). To propagate the fault effect to the circuit output: If Gate B's output is 0, Gate C's output will be 1, which is not distinguishable from the normal operation where Gate A's output is correctly functioning. If Gate B's output is 1, Gate C's output should be 0. If the circuit still outputs 1 despite Gate B's output being 1, it indicates the fault (stuck-at-1 at Gate A's output). To test this fault, set Z and W (inputs to Gate B) to values that make Gate B's output 1 (e.g., both 0 since it's a NAND gate), and observe the overall circuit output. If the output is not as expected (it should be 0 but is 1), it confirms the fault at Gate A's output.

(b) Testing Fault at NOR Gate A (Output Stuck at 0) Inputs to NOR Gate A: 0, 0 (to normally output 1, but it's stuck at 0). Inputs to NOR Gate B: Should be set to produce an output of 1 (0, 0), so the fault in Gate A (output stuck at 0) influences the output of the NAND gate. Input to NOT Gate: Should be set to 0 to produce a normal output of 1 (but it's stuck at 1). This ensures the NOT gate's normal operation doesn't mask the fault in Gate A. This setup will allow the fault in Gate A to propagate to the output 'o' via the NAND gate. Testing Fault at NOR Gate C (Output Stuck at 0) Inputs to NOR Gate A: Any combination that would normally produce a 0 (e.g., 1, 1). Inputs to NOR Gate B: Any combination that would normally produce a 0 (e.g., 1, 1). Input to NOT Gate: Should be set to 0 to produce a normal output of 1 (but it's stuck at 1). This setup will allow the fault in Gate C to be observable at the output 'o'. Testing Fault at NOT Gate (Output Stuck at 1) Inputs to NOR Gate A and B: Any combination, as we are testing the NOT gate. However, setting them to produce a 0 (e.g., 1, 1) would be ideal to observe the effect at the NAND gate. Input to NOT Gate: Should be 1 to normally produce an output of 0 (but it's stuck at 1). This setup allows the fault in the NOT gate to be observed at the output 'o'. Summary of one such Input Values for Each Fault: To test NOR Gate A's fault: NOR A: 0, 0; NOR B: 0, 0; NOT Gate: 0 To test NOR Gate C's fault: NOR A: 1, 1; NOR B: 1, 1; NOT Gate: 0 To test NOT Gate's fault: NOR A: 1, 1; NOR B: 1, 1; NOT Gate: 1 (c)

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For this circuit, let’s first try to test the fault at gate (f) whose output is stuck at 0. We need to give the input combinations to this gate (f) such as its output should be 1. Since f is a NOR gate, and NOR gate output is 1 only when both inputs are 0. So, m and c should be zero. Now, m is the output of NAND gate which can only be 0 when A and B both are 1. So, the input test vector will be A, B, C = 1,1,0 If we want to test the fault at NAND gate (A) output which is stuck at 1, we should give it input combinations such as it should be 0 which can be only possible when A, B =1,1. Now, if we want this fault to propagate to NOR gate(f) output then C should be zero. So, again test vector is A, B, C= 1, 1, 0.

2. (a) Draw the schematic of the logic circuit described by the Verilog code below: module pie( x, y, a, b, c); input a, b, c; wire t1, t2; output x,y; xor #2 x1(t1,a,b); not #1 n1(x,t1); and #3 a1(t2,x,c); or #3 o1(y,t2,b); endmodule The schematic of the above Verilog code. (b) What is the critical path of this design from primary inputs to outputs and what is the delay of the critical path in terms of unit delay? The critical path will be: a -> xor -> not -> and -> or -> y => 9 unit delay

3. Notice that the logic below consists of three repeated parts. (a) Write a Verilog explicit structural description of the logic which consists of two modules, one module, name it part- logic, will be for the part that’s repeated, the other, name it whole-logic, will instantiate part-logic three times and interconnect them appropriately. Write the part-logic using the Verilog primitives. Choose appropriate inputs and outputs for the two modules based on the diagram. (b) Repeat (a) by writing the part-logic using the continuous assignment statement. (a) Part-logic module: module part-logic(x,y,a,b,c); input a,b,c; output y,x; wire t1; not n1(t1,b); and a1(x,a,t1); or o1(y,x,c); endmodule Whole-logic module: module whole-logic(x,y,a,c,b); input [2:0] a; input [2:0] b; input c; output [2:0] x; output y; wire c1,c2; part-logic pl1(x[0],c1,a[0],b[0],c); part-logic pl2(x[1],c2,a[1],b[1],c1); part-logic pl3(x[2],c,a[2],b[2],c2); endmodule (b) Using continuous assignment statement. module part-logic(x,y,a,b,c); input a,b,c; output x,y; assign x = a & (~b); assign y = x | c;

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endmodule

4. The Hamming encode/decoder in the lecture detected and corrected one error bit. By adding a thirteen bit which is the exclusive-OR of the other twelve bits, double bit errors can be detected (but not corrected). Add this feature to the example and modify the noisy channel so that sometimes two bits are in error. Change the $display statement to indicate the double error. See the additional supplemental information about the 13-bit Hamming code. Please show all the Verilog codes for your design.

From TA: There are many possible implementations for this hamming code. If your logical concept matches with our requirement, then you can get a full credit. You Verilog code would be neither compliable nor synthesizable. // hamDecode, Brandon Lu blu006@ucr.edu module xor8 (xout, xin1, xin2); output [7:0] xout; input [7:0] xin1,xin2; xor(xout[7], xin1[7], xin2[7]), (xout[6], xin1[6], xin2[6]), (xout[5], xin1[5], xin2[5]), (xout[4], xin1[4], xin2[4]), (xout[3], xin1[3], xin2[3]), (xout[2], xin1[2], xin2[2]), (xout[1], xin1[1], xin2[1]), (xout[0], xin1[0], xin2[0]); endmodule module deMux (outVector, a, b, c, d, enable); input [7:0] outVector; input a, b, c, d, enable; wire m11, m10, m8, m6, m5, m4, m2; and (m11, ~a, ~b, c, d, enable), (m10, a, b, ~c, d, enable), (m9, ~a, b, ~c, d, enable), (m8, a, ~b, ~c, d, enable), (m6, a, b, c, ~d, enable), (m5, ~a, b, c, ~d, enable), (m4, a, ~b, c, ~d, enable), (m2, a, b, ~c, ~d, enable); assign outVector = {m11, m10, m9, m8, m6, m5, m4, m2}; endmodule module hamDecode (vIn, valueOut, error); input [12:0] vIn; output [7:0] valueOut; output error; wire c1, c2, c4, c8; wire [7:0] bitFlippers; xor (c1, vIn[0], vIn[2], vIn[4], vIn[6], vIn[8], vIn[10]), (c2, vIn[1], vIn[2], vIn[5], vIn[6], vIn[9], vIn[10]), (c4, vIn[3], vIn[4], vIn[5], vIn[6], vIn[11]), (c8, vIn[7], vIn[8], vIn[9], vIn[10], vIn[11]); deMux mux1 (bitFlippers, c1, c2, c4, c8, 1'b1); xor8 x1 (valueOut, bitFlippers, {vIn[11], vIn[10], vIn[9], vIn[8],

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vIn[6], vIn[5], vIn[4], vIn[2]}); assign error = ~^vIn & (c1 | c2 | c4 | c8); endmodule // hamDecode, Brandon Lu blu006@ucr.edu module hamEncode (vIn, valueOut); input [7:0] vIn; output [12:0] valueOut; wire h1, h2, h4, h8, hA; wire [11:0] preParity; xor (h1, vIn[0], vIn[1], vIn[3], vIn[4], vIn[6]), (h2, vIn[0], vIn[2], vIn[3], vIn[5], vIn[6]), (h4, vIn[1], vIn[2], vIn[3], vIn[7]), (h8, vIn[4], vIn[5], vIn[6], vIn[7]); assign preParity = {vIn[7:4], h8, vIn[3:1], h4, vIn[0], h2, h1}; assign hA = ^preParity; assign valueOut = {hA, preParity}; endmodule // hamDecode, Brandon Lu blu006@ucr.edu module testHam(); reg [7:0] original; wire [7:0] regenerated; wire [12:0] encoded, messedUp; wire error; reg [3:0] messUp; reg [3:0] messUpAgn; integer seed; initial begin seed = 53; forever begin original = $random(seed); messUp = $random(seed); messUpAgn = $random(seed); #1 if ((messUp <= 12 || messUpAgn <= 12) && (messUp != messUpAgn)) $display("original=%h, encoded=%h, messer=%4h,messed=%h, error=%b, regen=%h",original, encoded, (2 ** messUp) ^ (2 ** messUpAgn), messedUp, error, regenerated); // if it isn't working correctly if ((original != regenerated) && ~error) $fatal("original does not match regenerated"); end // forever begin end // initial begin hamEncode hIn (original, encoded); hamDecode hOut (messedUp, regenerated, error);

assign messedUp = encoded ^ (2 ** messUp) ^ (2 ** messUpAgn); endmodule VCS Result: