_LAB 2 - BOOLEAN LOGIC

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1100 B

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Apr 3, 2024

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LAB 2 - BOOLEAN LOGIC ITI 1100A- Digital Systems Winter 2024 School of Electrical Engineering and Computer Science University of Ottawa Course Coordinator: Dr. Hussein T. Mouftah Teaching Assistants: TA 1 Jainam TA 2 Delphi TA 3 Aseem Group 21 Ayaan Chaudhary 300373526 Youssuf Helaly 30035594 Experiment Date: February 8th 2024 Submission Date: February 19th 2024

Objectives ● Simplifying logic functions by beginning with their Boolean expressions or logic truth tables ● To create, put into practice, and evaluate reduced combinational circuits ● utilizing parameters to create and construct combinational logic circuits ● To put combinational circuits into practice with any kind of logic gate ● putting combinational circuits into practice with NAND gates alone. ● To simplify Boolean formulas and implement them as logic circuits using Karnaugh maps; ● To demonstrate that the sum-of-products (SOP) minimized circuit with NAND gates is equal to the product-of-sums (POS); ● to demonstrate the equivalence of the POS and the SOP. Equipment and Components ● Quartus II 13.0 Service-Pack ● Altera DE2-115 circuit board ● Solid-core wires ● Dell PC with Lenovo desktop Circuit Diagrams Part I – Combinational Logic Circuits minimization by Boolean Algebra Boolean expression :Y = (AB)’C D+ (A’+ B’)(CD)’+ (A’+ B’)’ can also be simplified to Y = (AB)’ + AB Figure 1: This one is the original simplified form of the expression above. The following circuit may also be considered:

Figure 2: The finished, reduced version of the expression where Y = 1 is represented by this circuit. Part II –Combinational Logic Circuits minimization by the Karnaugh Map Method Y = AB' + B'C'D' + ACD' + B'CD which reduces to Y = AB' + ACD' + B'D'. This simplified expression can be transformed into the following by applying NAND gates to convert it: Y = ((AB')'(B'D')'(ACD')')'. The circuit schematic below illustrates this expression. Figure 3: Screen-shot of the logic diagram of the SOP minimized circuit with NAND gates of the function Y(A, B, C, D) from Table 5.2.1. Part III – Design of Combinational Logic Circuits P = D3’D2’D1 + D3’ D2 D0 + D2 D1’ D0 + D2’ D1 D0. Having to convert this expression using NAND gates, the simplified expression can be changed to the following: P = ((D3’D2’D1)’(D3’ D2 D0)’(D2 D1’ D0)’(D2’ D1 D0)’)’. This expression is what the circuit diagram below is representing (Figure 5.2.2)

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Figure 4: Screen-shot of the block diagram of the prime number detector with only NAND Gates Part III – Design of Combinational Logic Circuit Simplest SOP representing figure 5.2.2 with any gates ( Boolean expression : P = D2D1’D0 + D3’ D2 D0 + D2 D1’ D0 + D2’ D1 D0 ) Figure 5: Screen-shot of the block diagram of the prime number detector as an SOP Experimental Data and Data Processing Part I – Combinational Logic Circuits minimization by Boolean Algebra Boolean expression: Y = (AB)’C D+ (A’+ B’)(CD)’+ (A’+ B’)’ simplified into Y = (AB)’ + AB

Figure 6: Simulation output waveform of Boolean expression : Y = (AB)’ + AB Table 1: Experimental data observed from Altera DE2-115 circuit board Input given from dip switches Observed Output from LED’s A B Y 0 0 1 0 1 1 1 0 1 1 1 1 Part I – Combinational Logic Circuits minimization by Boolean Algebra Boolean expression: Y = 1 Figure 7: Simulation output waveform of Boolean expression : Y = 1 Input given from dip switches Observed Output from LED’s VCC Y 0 1 1 1

Part II –Combinational Logic Circuits minimization by the Karnaugh Map Method SOP and POS minimized circuit with NAND gates Figure 8: Simulation output waveform logic diagram of the SOP and POS minimized circuit Table 2: Experimental data observed from Altera DE2-115 circuit board Input given from dip switches Observed Output from LED’s A B C D Y 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1

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1 1 0 0 0 1 1 0 1 0 1 1 1 0 1 1 1 1 1 0 Part III – Design of Combinational Logic Circuits Simplest SOP circuit that implements the block diagram of a prime number detector with AND Gates (Figure 5.2.2) Figure 9: Simulation output waveform logic diagram of the prime number detector with only NAND Gates (Same for simplest SOP) Table 3: Experimental data observed from Altera DE2-115 circuit board Input given from dip switches Observed Output from LED’s D3 D2 D1 D0 P 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 0

1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0 Comparison of Theoretical Data and Experimental Data Part I – Combinational Logic Circuits minimization by Boolean Algebra Boolean expression: Y = (AB)’C D+ (A’+ B’)(CD)’+ (A’+ B’)’ can also be simplified to Y = (AB)’ + AB Table 4: Comparison of Theoretical and Experimental results for Boolean expression : Y = (AB)’ + AB Inputs Expected Results Actual Results A B Y Y 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 1 The results observed experimentally for the Boolean expression: Y = (AB)’ + AB Circuit from the Altera DE2-115 circuit board were identical to results obtained theoretically as expected.

Part II –Combinational Logic Circuits minimization by the Karnaugh Map Method SOP minimized circuit of truth table of Part II logic function(Table 5.2.1) with NAND gates Table 5: Comparison of Theoretical and Experimental results for SOP and POS minimized circuit Inputs Expected Results Actual Results A B C D Y Y 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 1 1 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 1 1 1 1 1 1 0 0 The results observed experimentally for SOP and POS minimized circuit from the Altera DE2- 115 circuit board were identical to results obtained theoretically as expected. Part III – Design of Combinational Logic Circuits

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Simplest SOP circuit that implements the block diagram of a prime number detector(Figure 5.2.2)(Same for both diagrams) Table 6: Comparison of Theoretical and Experimental results for simplest SOP circuit that implements the block diagram of a prime number detector(Figure 5.2.2) Inputs Expected Results Actual Results D3 D2 D1 D0 P P 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 0 0 0 0 1 0 1 1 1 0 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 1 1 1 1 0 0 0 0 1 1 0 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 The results observed experimentally for Simplest SOP circuit that implements the block diagram of a prime number detector with AND Gates (Figure 5.2.2) from the Altera DE2-115 circuit board were identical to results obtained theoretically as expected. Discussion & Conclusions ● Throughout the course of the experiment, several aspects were observed and documented, including the utilization of the QUARTUS II software, the Altera DE2-115 circuit board, and the overall lab procedure. Also, we had to learn about the operation and interpretation of the circuit board's results.We figured out that when entering inputs into the circuit board, there were two possible outcomes for its output. The presence of a red LED light on the Altera DE2-115 indicated a false or 0 output, while the absence of light indicated a true or 1 output. Manipulating the Altera DE2-115 DIP switches also had different results. When the switch was in an upward position, it corresponded to a value of 1 or true. Conversely, pressing the switch down resulted in an output of false or 0. ● The expected and experimental findings are the same, as previously demonstrated. This indicates that there is no difference between the original and simplified Boolean

formulas. Since the outputs of their truth tables are the identical, this assumption can be made. For instance, a tautology was the expected outcome for the first lab section. Y was determined to be equal to 1 even when the Boolean statement was repeatedly simplified, indicating that it is a tautology. This was further demonstrated by theAltera DE2-115 circuit implementation, which demonstrated that all outcomes were accurate. ● Every major goal of the lab was accomplished. The intended logic circuits were created using QUARTUS II and the schematics. After that, they underwent functionality tests, and the results were recorded and contrasted with the anticipated data. The sub-objectives were also fulfilled during the course of the lab experiment. It was discovered that Karnaugh maps are a useful tool for locating simplified Boolean expressions. Afterwards, these streamlined formulations were employed for the duration of the experimental setup. It was found that the POS is equivalent to the SOP minimized circuit with NAND gates. This was determined in part two by implementing the SOP minimized circuit with NAND gates into the Altera DE2-115 card, and recording its outputs. When comparing these results with the truth table of the POS, it was found that they were identical. Therefore, it can also be stated that the POS and SOP Boolean expressions/circuits are equivalent. ● A few things that might have gone wrong in the lab were: connecting wires to the wrong pin and neglecting to recompile the project after each step of the process. The associated input value would not register if the wire was not in its designated pin on the circuit board, resulting in a set of data that did not reflect the circuit. Additional concerns that were observed have to do with software. Time was lost because there were issues accessing the QUARTUS II program. Time was lost and it was unclear whether the simulations were accurate because they were not performing as planned. Appendix (Pre-Lab)

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