Lab4_manual

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ECEN 248: Introduction to Digital Design Department of Electrical and Computer Engineering Texas A&M University Laboratory Exercise #4 Simple Arithmetic Logic Unit Lab exercise created and tested by: Cheng-Yen Lee, Kushagra Gupta, Myung Seok Shim, Abbas Fairouz Zhixing Li, Pierce Cantrell and Sunil P. Khatri

2 Laboratory Exercise #4 1 Introduction In this lab, you will design, implement, and test a simple 4-bit Arithmetic Logic Unit (ALU) which will perform elementary computations such as addition, subtraction, and bit-wise AND. To do so, you will learn about Two’s Complement arithmetic and multiplexers. 2 Background 2.1 Two’s Complement Arithmetic In the previous lab, we briefly introduced addition of unsigned numbers but made no mention of subtraction. In order to perform subtraction, we need a way to represent negative numbers in binary. Therefore, we will introduce a binary signed number representation and show how to use it for subtraction. Note that a binary signed number is simply a binary number that can take on either a positive or negative value. Although there are many ways to represent signed numbers in binary, we will only touch on one such representation in this lab assignment, namely Two’s Complement . First of all, how to compute two’s complement? Just invert all the bits and add 1 to it . Assume we have a 4-bit binary number that is 0101 , what is the two’s complement of it? 1. Invert all the bits: 0101 = 1010 2. Add 1 to the result: 1010 + 1 = 1011 3. Check sum: 0101 + 1011 = 10000 = 2 4 Thus the two’s complement of 0101 is 1011 , or we can say two’s complement of 5 is − 5 . Now you may have the question: 1011 should be 11 , how can it be − 5 ? Next, we are going to learn how to read two’s complement negative binary number. The leftmost bit indicates the sign of number: 0 means positive and 1 means negative. Positive numbers remain the same but negative ones do not. Let us go over the 4-bit binary number 1011 . 1. The leftmost 4th bit is 1 , which means it is negative. 2. Take two’s complement again to determine its magnitude: 1011 + 1 = 0101 = 5 decimal So 1011 is − 5 in two’s complement. To verify it, 0101 + 1011 = 10000 , which is 0 . Here, because we are doing 4-bit binary math, we do not care about the leftmost 5th bit, which is also a carry out bit 1 . 2 ECEN 248

Laboratory Exercise #4 3 Last but not least, there is a small trick for you to extend the original binary number to more bits. For positive numbers, fill the missing bits with 0’s and for negative numbers, fill the missing bits with 1s. 0101 and 1011 are extended to 6-bit numbers as below: 1. 0101 4 − bit = 000101 6 − bit 2. 1010 4 − bit = 111010 6 − bit Up till now, we have been able to represent both positive and negative in binary. Therefore, subtraction can be performed by negating the subtrahend and adding it to the minuend. Figure 1 illustrates the addition of two’s complement numbers. Figure 1: Addition of Two’s Complement Numbers The subtraction on the left generates the result correctly but the addition on the right does not! 1000 is − 8 in two’s complement, not 8 . This situation is called overflow because it exceeds the range of two’s complement. In mathematical terms, the decimal value of a two’s complement binary number belongs in [ − 2 n − 1 , 2 n − 1 − 1] , where n is the number of bits. Thus 4-bit two’s complement cannot represent decimal number 8 , which causes the overflow. Because the result is wrong when overflow has occurred, it must be indicated so that the wrong one can be discarded. For two’s complement arithmetic, overflow occurs when both input sign bits are the same but differ from the output’s sign bit. If there is still something unclear, please consult your text book and lecture slides. 2.2 Multiplexers A multiplexer (MUX for short) is a digital circuit which selects an output from more than one input. Figure 2 provides two such examples, where A , B , C , D , Output , and S are all 1-bit wide. Note that { S 1 , S 0 } represents the concatenation of S 1 and S 0 and is a 2-bit bus (i.e. grouping of signals noted by the diagonal line crossed through the arrow and marked with a “2”). The 2:1 MUX shown in Figure 2(a) outputs A if the selection line, S , is logic 0 and outputs B otherwise. Figure 2(b) depicts a 4:1 MUX which selects from four inputs, A , B , C , or D , based on the binary value ECEN 248 3

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4 Laboratory Exercise #4 (a) 2:1 MUX (b) 4:1 MUX Figure 2: Multiplexers of { S 1 , S 0 } . For example, when S 1 = 0 and S 0 = 0 (i.e. { S 1 , S 0 } =“00”), the value of input A is passed through to output . Likewise, when S 1 = 0 and S 0 = 1 (i.e { S 1 , S 0 } =“01” ), the value of input B is passed through. The previous examples depicted 1-bit wide multiplexers; however, it is often necessary to multiplex buses of signals. Figure 3 shows how a 2-bit MUX can be constructed from two 1-bit MUXs. The drawing on the left shows the two MUXs superimposed to create the 2-bit wide MUX on the right. Note that the selection signals, S , have been tied together. We can easily create n -bit wide MUXs in this manner. Figure 3: 2-bit Wide 2:1 MUX In this lab, we are using component SN74CT257N as our chip for the MUX. Its pin-out diagram is shown in Figure 4. The only thing needs to be noticed is that ¯ A/B is the select signal S and OE must be connected 4 ECEN 248

Laboratory Exercise #4 5 Figure 4: 4-bit 2:1 MUX SN74HCT257N to ground. For more information, please consult your data sheet. 2.3 Arithmetic Logic Unit The ALU is a component that is capable of performing various arithmetic and logical operations and is a fundamental building block of any sort of computational device. Simple microprocessors found in home appliances often contain only one ALU, while the modern Central Processing Units (CPUs) and Graphics Processing Units (GPUs) found in today’s desktops and mobile devices contain many very powerful ALUs. The symbol typically used to represent an ALU is shown in Figure 5. Figure 5: ALU Symbol A and B represent the n -bit input buses, while Result represents the output bus, which can be n -bits in size or greater. Not shown in this simple drawing are the control and status signals, which will be expounded upon shortly. One way to create a simple ALU is to build several computational blocks and multiplex the ECEN 248 5

6 Laboratory Exercise #4 output buses. The selection signals for the multiplexer then serve as the control signals for the ALU. Today we are going to build a simple ALU by ourselves. 3 Logic Design This section of the laboratory assignment will guide you through the design of a simple ALU capable of adding, subtracting, and bit-wise ANDing. 3.1 Adder & Subtractor Design The ALU design discussed earlier can be inefficient because certain ALU operations could share logic. For example, as we learned in the background section of this manual, addition and subtraction both utilize an adder circuit. If we naively designed our ALU, we could create a separate adder for addition and another one for subtraction. However, we can do better by constructing an addition/subtracting circuit as shown in Figure 6. Here you can see the only difference between our design and the 4-bit carry ripple adder are the XOR gates. Also the carry-in bit can select the function now. Figure 6: 4-bit Addition/Subtraction Circuit with Overflow Detection Remember that subtraction is simply addition in which the B operand is complemented. To take two’s complement of a binary number, we must invert all the binary digits and add one to the result. When feeding the carry-in signal with “Sub” as 1 , the circuit is performing XOR between B and 1111 . As we know, 6 ECEN 248

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Laboratory Exercise #4 7 1 ⊕ b = ¯ b . Thus it is a subtraction unit when “Sub” is logic 1 . Similarly, when “Add” is logic 1 it is an addition unit. In this lab, you do not have to build every single full adder on you own. Instead, we provide you the component SN74HC283E as the 4-bit carry ripple adder. All you need to do is to connect several XOR gates. 3.2 Multiplexer Design In this part, you don’t need to design anything because we will provide you the chip SN74CT257N with the 4-bit wide 2:1 MUX packed inside it. Reading over the background section will help you a lot. 3.3 4-bit ALU Design At this point, we have acquired all pieces we need to finish our simple ALU design which can do three operations: AND, addition and subtraction. Our last job is signal connection. Figure 7: Simple ALU Design Figure 7 is the block design diagram of our ALU. c 0 is the signal that selects AND or math function. c 1 is the signal that determines addition or subtraction. Note that there is a black box in Figure 7, which is the unit to detect overflow. We will use it later. 4 Lab Procedures For the lab procedures below, consult the datasheets of each component for the pin-outs and electrical/timing characteristics of these circuits. If you do not remember how to wire up the DIP switch and LEDs, read the background section of the lab 2 manual. Please note that the following experiments are leading you to build an ALU, so please organize the breadboard area in advance for your final design. ECEN 248 7

8 Laboratory Exercise #4 4.1 Experiment Part 1 In the first part, bread-board and test your addition/subtraction unit. To do so, we must utilize the 4-bit carry ripple adder component SN74HC283E. Because A and B are 4-bit signals, DIP switch is recommended. However, you will have to use a jump wire for the control signal. Display the output signals using LEDs. 4.2 Experiment Part 2 Test your 4-bit 2:1 MUX chip SN74CT257N using LEDs. 4.3 Experiment Part 3 1. Connect the outputs of AND units and addition/subtraction units to the ”A” and ”B” inputs, respec- tively, of the 4-bit 2:1 MUX. 2. Connect OE of the MUX to ground. 3. Use LEDs to display the result coming from the MUX. 4. Vary the control signals c 0 and c 1 by manually connecting them to power or ground. Verify the circuit operation matches the operation table created in the pre-lab. In the demonstration, you need to show AND, addition and subtraction function of you ALU. 5 Lab Deliverables 5.1 Pre-lab Deliverables Please include the following items in your pre-lab write-up. 1. Examples demonstrating how the circuit in Figure 6...,bnnnn adds and subtracts. 2. Truth table and minimized Boolean expression for a 1-bit wide 2:1 MUX. 3. Gate-level schematic for the final ALU design. 4. Create a table with three columns: c 0 , c 1 and OP, such that c 0 and c 1 correspond to the ALU control signals and OP is the operation it will perform, like AND. 8 ECEN 248

Laboratory Exercise #4 9 5.2 Post-lab Deliverables Please include the following items in your post-lab write-up. 1. Observe and fill in the Table 1. Both A and B are two’s complement numbers. The result should be a 4-bit binary number. Determine whether overflow occurs or not. 2. Determine the maximum gate delay through your final ALU circuit assuming each gate has a delay of 1 unit. Highlight the critical path on the gate-level schematic. 3. Please design the overflow detecting unit in Figure 7. You can use all available signals except the signals inside the chip package. Show your process and draw a gate-level schematic. Table 1: c 0 and c 1 operation. c 0 c 1 Operation A B Result Overflow 0 0 0100 0110 0 1 0110 1101 1 0 0100 0110 1 0 0100 1101 1 0 1101 1001 1 1 0100 0111 1 1 0110 1001 ECEN 248 9

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