lab5 Fall 2023-2

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ECEN 248: Introduction to Digital Design Department of Electrical and Computer Engineering Texas A&M University Laboratory Exercise #5 Introduction to Logic Simulation and Verilog Lab exercise created and tested by: Cheng-Yen Lee, Kushagra Gupta, Abbas Fairouz He Zhou, Joshua Mashburn, and Sunil P. Khatri

2 Laboratory Exercise #5 2 ECEN 248 1 Introduction In the previous labs, we tested and debugged our digital designs by bread-boarding the actual circuits using ICs. For small designs, this method proved to be quite effective, and in the late 1960’s and early 1970’s, this was standard practice. However, as the gate counts of our circuits increased, this method became far less attractive. Thankfully, with advances in computer technology, there are alternatives to bread-boarding circuits. In this day and age, we can effectively simulate the operation of our digital circuits during the design process without being burdened with the tedium you all have experienced up to this point. In lab this week, we will demonstrate the concept of digital circuit simulation and, in doing so, introduce Verilog ® HDL, an Institute of Electrical and Electronics Engineers (IEEE) standard Hardware Description Language (HDL). 2 Background The following subsections will provide you with some of the background necessary to understand and ap- preciate the way modern digital design is carried out. For a more in-depth treatment, please consult the course text book. 2.1 Verilog HDL Programming languages have proven to be effective for software development. Interestingly, a similar truth holds for hardware development. Just as programming languages boost developer productivity, Hardware Description Languages (HDLs) do so through various levels of abstraction, while providing a means to suc- cinctly describe digital circuits. What differentiates a traditional programming language from a standard HDL is the manner in which operations described within the language are handled. In a tradition program- ming language such as C, operations happen sequentially, and conditional statements facilitate changes in program flow. In contrast, the operations described in an HDL happen concurrently, and signals (often called nets) allow concurrent operations to interact with one another. In the 1980’s, two competing HDLs were developed, namely VHDL and Verilog. Today, both languages co-exist, encouraging tool vendors to support VHDL and Verilog simultaneously within a single design. For our work in this lab, we will concentrate on Verilog; however, it is important to note that many of the HDL principals demonstrated here apply to VHDL as well. Verilog offers various levels of abstraction for describing digital circuits with structural at the bottom and behavioral at the top. Any given design could have a mixture of these abstraction levels, but in this lab assignment, we will start at the lowest level and move up. The example shown below uses structural Verilog and the gate-level primitives built into Verilog to describe the 1-bit wide, 2:1 multiplexer (MUX) you designed in the previous lab. The corresponding

Laboratory Exercise #5 3 ECEN 248 3 \ ∗ ∗ \\ gate-level schematic in Figure 1 labels the module ports, internal wires, and gate instance names according to the provided Verilog code. Figure 1: Gate-level Schematic of a 1-bit wide, 2:1 MUX 1 ‘ t i m e s c a l e 1 ns / 1 ps / / Note : t h a t symbol i s a b a c k t i c k ( below Esc ) not a quote ‘ d e f a u l t n e t t y p e none 3 / * This module d e s c r i b e s a 1− b i t wide m u l t i p l e x e r u s i ng s t r u c t u r a l c o n s t r u c t s * * and gate − l e v e l p r i m i t i v e s b u i l t i n t o V e r i l o g . * / 5 module two one mux ( Y, A, B , S ) ; / / d e f i n e t h e module name and i t s i n t e r f a c e 7 / * d e c l a r e o u t p u t and i n p u t p o r t s * / 9 output wire Y; / / d e c l a r e o u t p u t o f t y p e wire input wire A, B , S ; / / d e c l a r e i n p u t s o f t y p e wire 11 / * d e c l a r e i n t e r n a l n e t s * / 13 wire not S ; / / i n v e r s e o f S wire andA ; / / o u t p u t o f and0 gate 15 wire andB ; / / o u t p u t o f and1 gate 17 / * i n s t a n t i a t e gate − l e v e l modules * / not no t 0 ( not S , S ) ; 19 and and 0 ( andA , not S , A ) ; and and 1 ( andB , S , B ) ; 21 or or 0 ( Y, andA , andB ) ; 23 endmodule / / d e s i g n a t e end o f module Syntactically, Verilog is very similar to the C programming language. Comments are designated in a similar fashion (i.e. / for comments which span multiple lines or for single line comments), and semicolons end declarations, assignments, and statements. Verilog is case-sensitive and all keywords are lowercase. The keyword, module , marks the beginning of the Verilog module, while the keyword,

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4 Laboratory Exercise #5 4 ECEN 248 endmodule , marks the end. In the example above, the module name is two one mux , and its ports are Y, A, B, and S. The port order is not enforced by the language but follows a common convention in which the output ports are first, followed by the input ports. The keyword, output , is used to declare a net as an output port, while input declares a net as an input port. Nets can be of type wire or reg . For now, we will only be concerned with wires. Nets can take on one of four values, namely ‘1’, ‘0’, ‘Z’, and ‘X’ for high, low, floating, and undefined, respectively. Modules, whether built-in or user-defined, are instantiated as seen in lines 14 through 19 of the code above. The module name is followed by the instance name. The instance name must obviously be unique; however, multiple instances of the same module may exist. Notice the order of ports for the built-in primitives (i.e. not , and , or ) follows the convention discussed above such that the output port is first, followed by the input ports. Since these operations are associative, the order of the inputs is not important. 2.2 Xilinx Vivado Xilinx ® Vivado Design Suite (Vivado ™ ) version 22.1 is the hardware development tool that we will be using in this laboratory. Xilinx manufactures a wide variety of re-programmable logic devices (we will discuss these further in the next lab) and supplies Vivado as a means to develop for these devices. Consequently, Vivado is an excellent teaching tool for modern digital design. It supports digital circuit simulation, which is the focus of this week’s lab assignment, in addition to all of the implementation processes necessary to load a design into a Xilinx device. It comes with an easy-to-use Graphical User Interface (GUI) and waveform viewer and supports both VHDL and Verilog. Xilinx Vivado is part of a larger class of computer-aided design (CAD) tools used to develop digital circuits. For additional information on Xilinx and Vivado 22.1, consult the manufacturer’s website at: www.xilinx.com 2.3 Linux OS Linux is an open-source Unix-like operating system (OS) commonly used in industry. The open-source license allows it to be used free of charge, which makes it a big win for the university setting. The Unix aspect allows Linux to be compatible with many of the CAD tools out on the market today. The Linux kernel along with the various support packages make up the specific Linux distribution. The machines in the ECEN 248 lab have a variant of Red Hat Linux called CentOS installed on them because many of the tool vendors will provide support for only Red Hat Linux and its derivatives. The CentOS Linux installation has a window manager, which gives you the look and feel similar to that of Windows or MacOS. However, the Linux terminal is available for those acquainted with Unix. As a result, you will be provided with commands to execute in the terminal throughout the lab session. Please try to understand what these commands do so that you can execute them in future labs without instruction. The format of the commands provided is shown below. The command to be executed follows the $ symbol. username@computername:˜$ command argument0 argument1

Laboratory Exercise #5 5 ECEN 248 5 → Note: Please ensure that you have a Unix account with the ECE department before arriving to your lab session. It is imperative that you are able to log into the CentOS machines in ECEN 248 lab 3 Pre-lab We will reuse the designs created in Lab 3 and Lab 4 for this week’s lab so no pre -lab submission is required. However, you will be expected to have the appropriate material ready for lab so please read over the entire lab manual before coming to your lab session. 4 Lab Procedures The lab experiments below will guide you through the development of a simple 4-bit ALU in Verilog using the Vivado Design suite. Each module that you create will be individually tested using the built-in digital circuit simulator, Vivado Simulator, with test bench files that we provide to you. 4.1 Experiment Part 1 The objective of this lab experiment is to familiarize you with the Vivado development environment. Please take note of what it is you are doing as you will be expected to perform similar exercises on your own in future experiments. 1. Launch Vivado and create a new design project. (a) Open a terminal window in the CentOS workstation by selecting Applications → System Tools → Terminal and type the following command and hit ‘Enter’ to create a work directory: mkdir ecen248 (b) Now execute the following commands to run Vivado: source /opt/coe/Xilinx/Vivado/2022.1/settings64.sh vivado The first command sets up the environment in order to run Vivado and the second command starts the Vivado suite. (c) Once Vivado loads, select File New Project The New Project Wizard will open. Click ‘Next’.

6 Laboratory Exercise #5 6 ECEN 248 Type a Project Name (ex.lab5) and a Project Location (ex. /home/ugrads/x/your-NetID/ecen248). Leave ’Create project subdirectory’ checked. Click ‘Next’ and select ‘RTL Project’. Click ‘Next’ and the ‘Add Sources’ window will appear. Select target language as ‘Verilog’ and sim- ulator language as ‘Verilog’. Click ‘Next’ until you reach the ‘Default Part’ window (shown below). Select ‘Boards’, scroll down, and select ‘Zybo Z7 - 10’ as shown below. Click ‘Next’ and select ‘Finish’ to create new project.

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Laboratory Exercise #5 7 ECEN 248 7 2. Next we will create a Verilog source file which describes the 2:1 MUX in Figure 1. (a) From within Vivado, select File → Add Sources to create a new file. (b) A window will appear as seen above. Type the name as ‘two one mux.v’ and save it into your lab 5 directory. You will see the text file opened in Vivado. (c) Type the Verilog code example found the in the Background section of this manual into the Vivado text editor window.

8 Laboratory Exercise #5 8 ECEN 248 Note: Do NOT copy and paste text from the PDF into the editor window. Symbols within the code do not always copy properly and will cause syntax errors when you attempt to build the project. 3. Add the 2:1 MUX source file and test bench to the Vivado project. (a) Right-click on the Design Sources within the Hierarchy window under Sources and select ‘Add Sources..’ as shown in below. (b) In the Add Sources window select ‘Add or create design sources’ and click ‘Next’. (c) Click on the green ‘+’ button and select ‘Add files’. Navigate to the source file you just created and hit ‘OK.’ Uncheck ”Copy sources into project” unless you are okay with your file being duplicated. Click ‘Finish’ to add the source file to the project. (d) Ensure the source file you just added appears under the Design Sources in the Hierarchy window. (e) Open a new terminal window (or tab) and copy the appropriate test bench file from the ECEN248 directory into you lab5 directory with the following commands: cd $HOME/ecen248/lab5 cp $HOME/VerilogFiles_Fall2021/248NeededFiles/two_one_mux_tb.v . The first command changes the current directory to your lab5 directory, while the second com- mand copies the 2:1 MUX test bench into the current directory. The ‘.’ at the end of the command is shorthand for the current directory.

Laboratory Exercise #5 9 ECEN 248 9 (f) Right-click on the Simulation Sources within the Hierarchy window under Sources and select ‘Add Sources...’ as shown earlier. (g) Add the ‘two one mux tb.v’ file to your Vivado project, leaving the source file properties as default again. (h) Ensure the hierarchy appears as seen below. (i) Open the 2:1 MUX test bench file (two one mux tb.v) and take a moment to examine the con- tents. The test bench utilizes advanced concepts in Verilog that we have not discussed yet, but some things should look familiar. A test bench file is nothing more than a Verilog module which instantiates the Unit Under Test (UUT) and stimulates the inputs for testing. Notice that the test bench module does not have any ports of its own. The input and output ports of the UUT are the focus, and when we simulate the test bench file, we will examine those signals. 4. Simulate the 2:1 MUX test bench. (a) To simulate a file using a test bench, right click on the test bench file you wish to simulate and select ‘Set as Top’. Here right click on ‘two one mux tb.v’ and make it top. (b) Select the 2:1 MUX test bench file in the hierarchy window and then click ‘Run Simulation’ from within the Flow Navigator panel. Select ‘Run Behavioral Simulation’. (c) If there are any errors or warnings, they will show up in the Console panel at the bottom of the screen (you may need to click the ”Console” tab). Correct any errors and warnings at this time. You may re-run the simulation process once you have fixed your source code. (d) The waveform panel shown below will open once your design successfully compiles. Take note of the waveform panel in the top-right corner and the console panel at the bottom. Along the left-hand side of the waveform panel, there is a toolbar with buttons. Find the Zoom Fit button

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10 Laboratory Exercise #5 10 ECEN 248 (the magnifying glass with a box drawn around it). Click this to fix the zoom and fit of your waveform. If your waveform panel is too small to read the waveform clearly, minimize the Scopes and Objects panels to the left of the waveform. Notice that the test bench exercises the multiplexer through all of the possible input combinations. Ensure that your design passes all of these tests. Please include a screenshot of the waveform in your lab report along with the console output of the test bench. 4.2 Experiment Part 2 The purpose of this experiment is to design the modules necessary to build our simple 4-bit ALU, while introducing a level of abstraction available in Verilog. Each component will be tested using Vivado with the provided test benches. You may need to look back at Experiment 1 if you forgot how to perform a procedure listed below in Vivado. 1. Figure 2 illustrates how to connect four 1-bit, 2:1 multiplexers together to create a single 4-bit, 2:1 multiplexer. This diagram should reflect the bread board circuit from the previous lab. (a) Using the above diagram and the code below as a starting point, describe a 4-bit, 2:1 multiplexer, which uses the module you created in Experiment 1.

Laboratory Exercise #5 11 ECEN 248 11 Figure 2: 4-bit wide, 2:1 MUX 1 ‘ t i m e s c a l e 1 ns / 1 ps ‘ d e f a u l t n e t t y p e none 3 / * This module c o n n e c t s f o u r 1− b i t , 2 : 1 MUXs t o g e t h e r t o * * c r e a t e a s i n g l e 4− b i t , 2 : 1 MUX * / 5 module f o u r b i t m u x ( Y, A, B , S ) ; 7 / * d e c l a r e o u t p u t and i n p u t p o r t s * / 9 / / o u t p u t i s a 4− b i t wide wire input wire [ 3 : 0 ] A, B ; / / A and B are 4− b i t wide wires 11 input wire S ; / / s e l e c t i s s t i l l 1 b i t wide 13 / * i n s t a n t i a t e user −d e f i n e d modules * / two one mux MUX0(Y[ 0 ] , A[ 0 ] , B [ 0 ] , S ) ; 15 two one mux MUX1(Y[ 1 ] , A[ 1 ] , B [ 1 ] , S ) ; / / you need two more module i n s t a n t i a t i o n s here . . . 17 endmodule (b) Add the file you just created to your current Vivado project. (c) Copy the appropriate test bench file, ‘four bit mux tb.v’, into your lab5 directory. As a refresher, the commands to do so may be found below. cd $HOME/ecen248/lab5 cp $HOME/VerilogFiles_Fall2021/248NeededFiles/four_bit_mux_tb.v . Note: If you use the same terminal that you used to do the last copy, you do not need to execute the first command! (d) Add the test bench that you just copied over to your Vivado project and simulate the logic behavior as you did in the previous experiment. To simulate four bit mux tb.v, right click on

12 Laboratory Exercise #5 12 ECEN 248 | | the file in the Hierarchy and select ‘Set as Top’. Please include a screenshot of the waveform in your lab report along with the console output of the test bench. 2. In the previous steps, we used structural Verilog to describe a 1-bit, 2:1 MUX. Then we used structural Verilog again to create a 4-bit, 2:1 MUX from our 1-bit MUX module. For the addition/subtraction unit, we will start with a slightly higher level of abstraction available in Verilog, commonly referred to as dataflow. The following steps will guide you through the process. (a) The assign statement in Verilog allows us to describe how data should flow from one wire to the next using arithmetic and logic operators available in most programming languages. The operand and result wires can be an arbitrary width; however, the width of each wire should match the operation being performed. For example, if you are describing a bit-wise AND operation on two 4-bit wires ( assign Result = A & B; ), the result wire should be 4-bits in width as well. Using the gate-level schematic for a full-adder illustrated in Figure 3 and the code snippet below as a template, describe a full-adder in Verilog using dataflow abstraction. Hint: The full-adder schematic provides suggested intermediate signal names. ‘ t i m e s c a l e 1 ns / 1 ps 2 ‘ d e f a u l t n e t t y p e none / * This module d e s c r i b e s t h e gate − l e v e l model o f * 4 * a f u l l −adder i n V e r i l o g * / 6 module f u l l a d d e r ( S , Cout , A, B , Cin ) ; 8 / * d e c l a r e o u t p u t and i n p u t p o r t s * / / / 1− b i t wires 10 input wire A, B , Cin ; / / 1− b i t wires 12 / * d e l c a r e i n t e r n a l n e t s * / wire andBCin , andACin ; / / 1− b i t wires ( missing something ???) 14 / * use d a t a f l o w t o d e s c r i b e t h e gate − l e v e l a c t i v i t y * / 16 a s s i g n S = A ˆ B ˆ Cin ; / / t h e hat ( ˆ ) i s f o r XOR a s s i g n andAB = A & B ; / / t h e ampersand (&) i s f o r and 18 / / f i l l i n code f o r andBC , andAC a s s i g n Cout = andAB andBCin ; / / p i pe ( ) i s f o r or 20 / / oh btw , t h e above l i n e i s missing something . . . 22 endmodule (b) Copy over the full- adder test bench file, ‘full adder tb.v’, from the course directory and add it to your current Vivado project. Simulate the full-adder design and ensure it works properly. Include a screenshot of waveform in your lab report along with the console output from the test bench.

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Laboratory Exercise #5 13 ECEN 248 13 Figure 3: Full-Adder Gate-level Schematic Figure 4: Addition/Subtraction Unit (c) Now that we understand the basics of structural and dataflow Verilog, we can use a mixture of the two abstraction levels to create the addition/subtraction unit found in Figure 4. As with the previous procedures, use the code below as a starting point. Note the new module description in lines 7-13. Verilog supports declaring and defining module ports in the same lines of code seen in the template.

14 Laboratory Exercise #5 14 ECEN 248 1 ‘ t i m e s c a l e 1 ns / 1 ps ‘ d e f a u l t n e t t y p e none 3 / * This V e r i l o g module d e s c r i b e s a 4− b i t a d d i t i o n / s u b t r a c t i o n * * u n i t u s i ng f u l l −adder modules which have a l r eady been * 5 * designed and t e s t e d . * / 7 module a d d s u b ( / * d e c l a r e o u t p u t and i n p u t p o r t s * / 9 output wire [ 3 : 0 ] Sum , / / 4− b i t r e s u l t output wire Overflow , / / 1− b i t wire f o r o v e r f l o w 11 input wire [ 3 : 0 ] opA , opB , / / 4− b i t operands input wire op Sel / / op Sel = 1 f o r s u b t r a c t 13 ) ; / / i n Verilog , we can d e s c r i b e a module i n t e r f a c e i n t h i s manner as w e l l ! 15 / * d e c l a r e i n t e r n a l n e t s * / wire [ 3 : 0 ] not B ; 17 wire c0 , c1 , c2 , c3 ; 19 / * c r e a t e complement l o g i c * / a s s i g n not B [ 0 ] = opB [ 0 ] ˆ op Sel ; / / i f op Sel == 1 , complement 21 / / f i l l i n t h e r e s t . . . 23 / * wire up f u l l adders t o c r e a t e a r i p p l e carry adder * / f u l l a d d e r a d d e r 0 ( Sum [ 0 ] , c0 , opA [ 0 ] , not B [ 0 ] , op Sel ) ; 25 / / something goes here . . . f u l l a d d e r a d d e r 3 ( Sum [ 3 ] , c3 , opA [ 3 ] , not B [ 3 ] , c2 ) ; 27 / * o v e r f l o w d e t e c t i o n l o g i c * / 29 a s s i g n Overflow = ; / / f i n i s h t h i s l i n e 31 endmodule (d) Copy ‘add sub tb.v’ from the course directory into your lab5 directory and simulate the test bench. As with the previous simulations, include the waveform and console output of the test bench simulation in your lab report. 4.3 Experiment Part 3 For this experiment, you will use your newfound Verilog skills to create the simple 4-bit ALU described in the previous lab. 1. Using your corrected block diagram of the 4-bit ALU from the previous lab submission, create a top-level module with the following interface: 1 ‘ t i m e s c a l e 1 ns / 1 ps ‘ d e f a u l t n e t t y p e none 3 module f o u r b i t a l u ( output wire [ 3 : 0 ] R e s u l t , / / 4− b i t o u t p u t

Laboratory Exercise #5 15 ECEN 248 15 | ≥ | 5 output wire Overflow , / / 1− b i t s i g n a l f o r o v e r f l o w input wire [ 3 : 0 ] opA , opB , / / 4− b i t operands 7 / * c t r l | o p e r a t i o n * * 00 | AND * 9 * 01 | ADD * * 10 | AND * 11 * 11 SUB * / input wire [ 1 : 0 ] c t r l ; / / 2− b i t o p e r a t i o n s e l e c t 13 ) ; Hint: Your code should instantiate the 4-bit, 2:1 MUX and the addition/subtraction unit which you have already designed. 2. Copy the 4- bit ALU test bench, ‘four bit alu tb.v’, file from the course directory and add it to your current Vivado project. 3. Simulate the test bench and add the appropriate material to your lab submission. Demonstrate your progress to the TA once your circuit simulates properly without errors or warnings. 4. (Honors) In the last lab, we asked that you add a signal to your ALU which is asserted HIGH when performing a subtraction and A B . Using the module interface below and a guide, modify your ALU to include this wire. Read ‘four bit alu tb.v’ carefully and try to understand each line. Modify ‘four bit alu tb.v’ to test the new added wire in your ALU and simulate your modified ALU with the modified testbench. 1 module f o u r b i t a l u h o n o r s ( output wire [ 3 : 0 ] R e s u l t , / / 4− b i t o u t p u t 3 output wire Gteq , output wire Overflow , / / 1− b i t wire f o r o v e r f l o w 5 input wire [ 3 : 0 ] opA , opB , / / 4− b i t operands / * c t r l | o p e r a t i o n * 7 * 00 | AND * * 01 | ADD * 9 * 10 | AND * * 11 SUB * / 11 input wire [ 1 : 0 ] c t r l / / 2− b i t o p e r a t i o n s e l e c t ) ; 5 Post-lab Deliverables Please include the following items in your post-lab write-up in addition to the deliverables mentioned in the Policies and Procedures document. 1. Include the source code with comments for all modules you simulated. You do not have to include test bench code. Code without comments will not be accepted!

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16 Laboratory Exercise #5 16 ECEN 248 2. Include screenshots of all waveforms captured during simulation in addition to the test bench console output for each test bench simulation. Please ensure these are legible in your report. Waveforms need to be properly fit. 3. Examine the 1-bit, 2:1 MUX test bench code. Attempt to understand what is going on in the code. The test bench is written using behavioral Verilog, which reads much more like a programming language. Explain briefly what it is the test bench is doing. 4. Examine the 4-bit, 2:1 MUX test bench code. Are all of the possible input cases being tested? Why or why not? 5. In this lab, we approached circuit design in a different way compared to previous labs. Compare and contrast breadboarding techniques with circuit simulation. Discuss the advantages and disadvantages of both. Which do you prefer? Similarly, provide some insight as to why HDLs might be preferred over schematics for circuit representation. Are there any disadvantages to describing a circuit using an HDL compared to a schematic? Again, which would you prefer. 6. Two different levels of abstraction were introduced in this lab, namely structural and dataflow. Provide a comparison of these approaches. When might you use one over the other? 6 Important Student Feedback The last part of the lab requests your feedback. We are continually trying to improve the laboratory exercises to enhance your learning experience, and we are unable to do so without your feedback. Please include the following post-lab deliverables in your lab write-up. Note: If you have any other comments regarding the lab that you wish to bring to your instructor’s attention, please feel free to include them as well. 1. What did you like most about the lab assignment and why? What did you like least about it and why? 2. Were there any sections of the lab manual that were unclear? If so, what was unclear? Do you have any suggestions for improving the clarity? 3. What suggestions do you have to improve the overall lab assignment?

lab5 Fall 2023-2

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