PR4

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School

Kansas State University *

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641

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Electrical Engineering

Date

Apr 3, 2024

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Spring 2024 ECE 641 – Advanced Digital Design Project 4 Objective: In this lab, you will SPI Slave that communicates with a SPI Master, which at the current time will be based on the Analog Discovery 2 board. The SPI Slave will only receive 4-byte words of data and store them in registers for DPRAM inside your digital design. There will be a 1-byte command (instruction) for each data transfer, and the command byte will be used as an address to specify the register location. Your digital design should have a way to display the partial contents of the write registers 0-7. Three DIP switches can be used with a data MUX to select which register to show on the 7-sgement displays. See the diagram below. Your designs will be verified by both Modelsim simulations as well by programming one of the following DE2 boards located in laboratory 2192. Altera Board FPGA & device Latest Quartus Lite/Web Version Supported DE2-115 Cyclone IV EP4CE115F29C7 Quartus 17.1

Activities : 1. Implement the SPI Slave as discussed in class. Plan to utilize a 1 byte command and 4 bytes of data. The command bit will have 8 bits which will be the address of the target register. 2. Add a set of write registers, all 32-bits in width. As a minimum make 8 registers. 3. Incorporate a data mux with selector bits from dip switches and data bus inputs from the write registers. The output of the data mux should go to 7-segement decoders and corresponding displays. This will allow you to view the contents of any of the write registers. 4. Simulate your design functionality with the provided testbench. Test write capabilities for multiple addresses. Provide screen snips of at least one case of both a write and a read transaction. 5. Compile your project in Quartus and make sure you address any errors (and hopefully most/all warnings). Do PIN assignments and program the board. The SPI signals should be mapped to the GPIO expansion header on the board. 6. Validate your programmed design using the AD2 SPI protocol interface. You can start out by just transferring 4 bytes of data, and then try using a floating point to binary/hex converter. a. Use the AD2 SPI Protocol functionality to perform write and read transactions. Typically DIO0 = CS, DIO1=SCLK, DIO2=MOSI, and DIO3=MISO. Below is an example of how to write 0x87654321 to register 0x03. 7. Save some photos and/or screen snips as evidence of your working design. Turn in a short report a. Scope of the project (short description) b. Your design strategy (hierarchy, layout, module names, etc.), and analysis of your design c. Results i. % of FPGA used or # of LE’s based on Quartus Compilation Report ii. Timing report from Quartus iii. Simulation results iv. Observations (photos) from lab tests d. What you learned e. Conclusions f. Appendix: source code DUE: Report 11:59 pm Wednesday, February 28 TURN IN: (prefer electronic submission of report (including Verilog code) through the Gradebook at K-State Canvas) POINTS: 3 0

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