Lab1 Report

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Boise State University Electrical and Computer Engineering Department EE230L: Digital Systems Laboratory Lab 1: Verilog Logic and XOR Checking Project Group: Team 15 Team Members: Carson Keller, Luke Duncan Experiment Date: 01/23/2024 Week 3 Report Due: 01/28/2024

Verilog Logic and XOR Checking ECE 230L 1 Objective The purpose of this lab was to gain further experience in Vivado, creating block designs, coding in Verilog, and running simulations, as well as further exploring logic gates, particularly exclusive-OR (XOR) gates, as a means of implementing circuit logic. 2 Content Overview In this lab, we created a circuit block design given provided prompts. Ultimately, these prompts were designed to spur consideration of gate logic and to challenge us to design circuits in accordance with stated circuit outcomes. We then implemented and completed a mostly pre-written Verilog wrapper program to be able to run a simulation of our block design which then allowed us to check the accuracy of our logic. 2.1 Content As previously stated, our block design was entirely based on predetermined prompts provided in the lab documentation. Our work and logic for each prompt were created as follows and corroborated with the corresponding truth tables: 1. LD0 = SW0 & SW1 & SW 2 The output of LED named LD0 will light if and only if all the three input switches named SW0, SW1, and SW2 are in the on (up) position. To implement this prompt we were instructed to use a XUP 3-input AND gate to which we attached all 3 named input switches with its output going to LD0. The block design of the prompt is detailed below with the following logic table: Table 1: LD0 Truth Table Figure 1: LD0 Block Design SW0 SW1 SW2 SW0 & SW1 (SW0 & SW1) & SW2 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 1 0 1 1 1 1 1 2. LD1 = SW0 | SW1 & BNTC The output LED named LD1 will light if both SW1 is on and the center button BTNC is pushed. It will also light if SW0 is on not matter what we do with SW1 or BTNC. To implement this prompt, we were instructed to use an XUP 2-input AND gate to which we attached SW1 and BNTC as inputs and an XUP 2-input OR gate to which we attached SW0 and the output of the AND gate as inputs with its output going to LD1. The block design of the prompt is detailed below with the following logic table: Page 2 of 9

Verilog Logic and XOR Checking ECE 230L Table 2: LD1 Truth Table Figure 2: LD1 Block Design SW0 SW1 BTNC SW1 & BTNC (SW1 & BTNC) | SW0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 3. LD2 = SW0 ^ SW1 LD2 will light if SW0 and SW1 are opposite values, but not if SW0 and SW1 are the same. To implement this prompt, we were instructed to use an XUP 2-input XOR gate to which we attached SW0 and SW1 as inputs with its output going to LD2. The block design of the prompt is detailed below with the following logic table: Table 3: LD2 Truth Table Figure 3: LD2 Block Design SW0 SW1 SW0 ^ SW1 0 0 0 0 1 1 1 0 1 1 1 0 4. LD3 = SW0 ^ SW1 ^ SW2 LD3 will light if and only if an odd number of the three switches SW0, SW1, and SW2 are on. In a later lab, we will see that this function is useful to calculate the sum bit S of a full adder. To implement this prompt, we were instructed to use two XUP 2-input XOR gates to which we attached SW0 and SW1 as inputs to the first and the output of that and SW2 as inputs to the second with its output going to LD3. The block design of the prompt is detailed below with the following logic table: Table 4: LD3 Truth Table Figure 4: LD3 Block Design SW0 SW1 SW2 SW0 ^ SW1 (SW0 ^ SW1) ^ SW2 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 0 0 0 Page 3 of 9

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Verilog Logic and XOR Checking ECE 230L 1 1 1 0 1 5. LD4 = SW0 & SW1 | SW1 & SW2 | SW0 & SW2 LD4 will light if and only if two or more of the three switches SW0, SW1, and SW2 are on. In a later lab, we will see that this function is useful to calculate the carry-out bit (Cout) of a full adder. To implement this prompt, we were instructed to use an XUP 3-input OR gate along with three XUP 2-input AND gates. To three of the AND gates, we attached SW0 and SW1, SW1 and SW2, and SW2 and SW0 respectively before feeding their outputs into the OR gate’s inputs. The block design of the prompt is detailed below with the following logic table: Figure 5: LD4 Block Design Table 5: LD4 Truth Table SW0 SW1 SW2 SW0 & SW1 SW1 & SW2 SW0 & SW2 (SW0 & SW1) | (SW1 & SW2) | (SW0 & SW2) 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 6. LD5 = ~(~SW0 | ~SW1| ~SW2) The expression in parentheses is true if any of the three switches are off. So LD5 is lit if it is not true that any of the switches are off. This is logically the same as saying all the switches are on. This is another way of calculating the 3-way AND as in item 1 above. To implement this prompt, we were instructed to use an XUP 3-input OR gate to which we attached three XUP 1-input INV gates as inputs, each with a different switch as an input, with the output of the OR gate passing through another INV gate before going to LD5. The block design of the prompt is detailed below with the following logic table: Page 4 of 9

Verilog Logic and XOR Checking ECE 230L Figure 6: LD5 Block Design Table 6: LD5 Truth Table SW0 SW1 SW2 ~SW0 ~SW1 ~SW2 ~SW0 | ~SW1| ~SW2 ~ (~SW0 | ~SW1| ~SW2) 0 0 0 1 1 1 1 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 0 1 1 1 0 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 1 1 0 1 1 1 0 0 0 0 1 7. LD6 = LD5 ~ ^ LD0 Since LD0 and LD5 are logically the same, LD5 ^ LD0 should always be false and LD5 ~ ^ LD0 should always be true. If LD6 is ever 0 in simulation or the LED named LD6 is ever off while flipping switchesSW0, SW1, or SW2 on the Basys 3 board, there is an error. LD0 is known as a sum-of-products (SOP) implementation and LD5 as product-of- sums (POS) implementation. To implement this prompt, we were instructed to use an XUP 2-input XNOR gate to which we attached the outputs heading to LD0 and LD5 as inputs with LD6 as the output. The block design of the prompt is detailed below with the following logic table: Table 7: LD6 Truth Table Figure 7: LD6 Block Design LD0 LD5 LD5 ~ ^ LD0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 1 1 Page 5 of 9

Verilog Logic and XOR Checking ECE 230L With our individual block designs conglomerated into a single design, it resulted in the following, conglomerated block design with all individual components present and included per instruction: Figure 8: Complete Block Design All LEDS stemmed from the same three input switches upon their conglomeration, with the exception of LED 1 which had an additional button input. This yielded an intricate web of interconnected gates and logic needing to be tested. To achieve this, we implemented and completed the provided, mostly pre- written wrapper (the code for which is included in the Appendices at the end of this report) and ran a simulation. The results of the simulation can be found in the form of the waveform figure that shows matching output between our design and the expected results as shown in Figure 9 below: Figure 9: Waveform Result Page 6 of 9

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Verilog Logic and XOR Checking ECE 230L As aforementioned, the Verilog Test Bench used to create the waveform in Figure 9 can be found in the Appendices. This waveform yields the results of the test. If the waveform output of leds[6:0] matches the expected output of expect_led[6:0], as ours does, this is considered a successful test, and we can conclude that our block design was constructed successfully. 2.2 Results Our expected outputs, as modelled in our truth tables, matched the outputs provided by the waveform simulation, showing that our designs are functioning as intended. What is the significance of the XNOR gate? What does this show about the logic connected to the inputs of this gate? The XNOR gate only has an output value of 1 if all inputs are passing in the same value. Since LD0 and LD5 are logically equivalent, the output of LD6 should always be 1. This allows LD6 to act as a control since if LD6 ever outputs 0, then there must be an error in either LD0 or LD5. 3 Conclusions Throughout this lab, our focus was on attaining more experience with creating block designs using various gates, such as the XNOR gate, and how the output of those gates can be represented in a truth table as discussed in lecture. We also gained a little experience writing code for the Verilog test bench. Write about what was learned, any problems faced and additional commentary not included in the content sections above. This is where you have the opportunity to reflect on the lab and consider how what you have done connects with what you have learned in lecture. Page 7 of 9

Verilog Logic and XOR Checking ECE 230L 4 Appendices The following appendices include material(s) referenced throughout the report not included in the text thereof for review and further consideration. 4.1 Verilog Test Bench `timescale 1ns / 1ps module lab01_tb( ); // test bench has no inputs or outputs reg [2:0] switches; // Switch values to drive the design reg btnc; // Pushbutton wire [6:0] leds; // LED values returned from design reg [6:0] expect_led; // Expected LED values calculated by TB integer i; // A loop index design_1_wrapper dut( // Instantiate your design .LD0(leds[0]), // Attach your output port LD0 to leds[0], etc. .LD1(leds[1]), .LD2(leds[2]), .LD3(leds[3]), .LD4(leds[4]), .LD5(leds[5]), .LD6(leds[6]), .SW0(switches[0]), // Attach your output port SW0 to switches[0] .SW1(switches[1]), .SW2(switches[2]), .BTNC(btnc)); // End of design instantiation function [6:0] expected_led; // Function to calculated expected values input [2:0] swt; input btc; // Function takes four input values begin expected_led[0] = swt[0] & swt[1] & swt[2]; expected_led[1] = swt[0] | swt[1] & btc; expected_led[2] = swt[0] ^ swt[1]; expected_led[3] = swt[0] ^ swt[1] ^ swt[2]; expected_led[4] = swt[0] & swt[1] | swt[1] & swt[2] | swt[0] & swt[2]; expected_led[5] = ~(~ swt[0] | ~ swt[1] | ~ swt[2]); expected_led[6] = leds[5] ~^ leds[0]; end endfunction // Step through switches = 0b’0000, 0b’0010, 0b’0100, 0b’0110, ... // Note: this does not test output when SW0 = 1 initial // An initial block runs once start to finish begin #10 btnc = 0; for (i=0; i<8; i=i+1) // i = 0, 1, 2, ... , 7 begin #20 switches = i; // wait 20ns, set switches to binary of i #10 expect_led = expected_led(switches,btnc); // wait 10ns, call func end #10 btnc = 1; for (i=0; i<8; i=i+1) // i = 0, 1, 2, ... , 7 begin #20 switches = i; // wait 20ns, set switches to binary of i #10 expect_led = expected_led(switches,btnc); // wait 10ns, call func end #50; Page 8 of 9

Verilog Logic and XOR Checking ECE 230L $finish; end endmodule Page 9 of 9

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