EECS 3100 Lab 7 Report

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University of Toledo *

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3100

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Electrical Engineering

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Feb 20, 2024

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Lab Report Experiment 7 Traffic Light Controller EECS 3100 Embedded Systems Lab By Collin Oedy (50%) & Nicholas Walsh (50%) 12/1/23
Introduction This is the final lab of the semester. The lab involves creating a control system for a two- street traffic light and crosswalk by implementing a finite state machine. Skills learned include advanced indexed addressing, linked data structures, and creating fixed time delays using the SysTick Timer. Pre-Lab There was a pre-lab reading assignment to be completed before starting the lab. Procedure First, we had to decide on the ports we would use for our system. We ultimately decided on option 1, where PA7, PA6, and PA5 would act as red south, yellow south, and green south. PA4, PA3, and PA2, would act as red west, yellow west, and green west. With this selection, we had to use option 2 for the sensors, so PE2, PE1, and PE0 would be walk sensor, south sensor, and west sensor. Next the Finite State Machine was designed. Below in Figure 1 is the drawing of the FSM. Figure 1: Finite State Machine Diagram Next, the program was developed. The program can be seen in its entirety below in Figure 2 .
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Figure 2: C Code of the Finite State Machine After, the circuit was to be built. Below in Figure 3 is the diagram of the circuit. Unfortunately, I have no pictures of the physical circuit as I forgot to take them before returning my breadboard.
Figure 3: Circuit Diagram After verifying the function of the circuit, the lab was completed. Discussion Below in Figure 4 , the logic analyzer for can be seen showing various states.
Figure 4: Logic Analyzer Output Finally, in Figure 5 , the different modes of operation can be seen. As stated earlier, I failed to take pictures of the physical circuit, so I simulated the outputs instead. Figure 5: East/West, Norh/South, and Walk operation
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Conclusion This final lab put most of the skills we had learned throughout the semester to the test, as well as teaching the workings of the finite state machine. Below in Figure 6 , the Demo record can be seen. The total score should be an 18.5, but the rest was cut off. Figure 6: Demonstration Record