ECE 429 lab 9 report

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Feb 20, 2024

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ECE 429 Laboratory Report #9 Standard Cell Based ASIC Design Flow By Phu Trinh ECE 429-L01 Prof. Ken Choi TA: Victoria Kim Lab date: 11/09/2022 Due date: 11/16/2022

Introduction This lab will provide a chance to learn and practice more circuit design techniques and tools that are often used in the industry to convert hardware description language into a layout in the ASIC design flow process. Using tools and libraries from several vendors, this tutorial walks you through the common cell-based ASIC design flow. An 8-bit accumulator design will be implemented using the OSU standard cell library from FreePDK45. The Synopsys Design Compiler will be used to initially synthesize the design, and the Cadence Encounter Digital Implementation System will be used to conduct place and route. The Synopsys Formality equivalence checker will be used to confirm the final design after the final layout has been painted in the Cadence Virtuoso platform. Theory and Pre-lab Theory The theory behind this lab is to create circuit layouts automatically by converting hardware description language into layout via the standard cell-based ASIC design flow. Various tools and libraries from different vendors such as OSU standard cell library, Synopsys Design Compiler, Synopsys Formality, Cadence Encounter Digital Implementation System, and Cadence Virtuoso will be introduced. Preliminary questions After reading through the lab manual and carefully reviewing Tutorial IV, specific topics such as Verilog code and testbench for 8-bit accumulator, how to set up logic synthesis and place & route, and equivalence checking were then studied to prepare for the lab session. Implementation First, RTL simulation was performed for the 8-bit accumulator by creating two Verilog files, one was the RTL code for the 8-bit accumulator, while the other one was the testbench for that 8-bit accumulator. When simulating the RTL programs using the command “ xrun accu_test.v accu.v +access+r ”, the output obtained was as follows:

Figure 1: RTL Simulation result of 8-bit accumulator. In the figure, it can be seen that after every 10ns, the accumulator was incremented by 1, which was the behavior specified in the Verilog testbench file. Therefore, the Verilog 8-bit accumulator was created successfully and showed the desired behaviors. When trying to use the Cadence SimVision platform to observe the waveforms of the Verilog testbench, the output obtained was as follow. Figure 2: Simulation waveform of the 8-bit accumulator testbench

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Comparing the outputs obtained in Figures 1 and 2, it can be seen that the outputs are consistent with each other, indicating that the circuit works fine. It can also be observed in figure 2 that the output was changed at every rising clock edge. After the RTL level design was verified, the next step was to synthesize the Verilog program into gate-level netlist that contains only interconnected standard cells. The output of the logic synthesis process is as follows: Figure 3: Logic Synthesis result

Figure 4: Estimation of cell areas after logic synthesis process.

Figure 5: Timings of the circuit netlist generated.

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Figure 6: Power report circuit of the circuit netlist generated. When trying to simulate the circuit netlist just generate using the previously created testbench of the 8-bit accumulator, the output came out to be Figure 7: Interconnected standard cells simulation result of 8-bit accumulator. Comparing the outputs obtained in figure 7 with figure 1, it can be concluded that the circuit specified in the netlist has the same behaviors as the RTL 8-bit accumulator previously created. After verifying the standard cells netlist, the next step was to place and route them for the final layout using Encounter platform. The result was that the GDSII steam file “finals.gds2” and an equivalent Verilog model “final.v” were created. The outputs were as follows:

a) b) Figure 8: Place and route Result using encounter a) Place and route Result and area report; b) Power report of the circuit.

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Wh Through the logic synthesis process, the netlist named “accu.vh” was created that contains the interconnected standard cells of the 8-bit accumulator circuit. When simulating the netlist using the Verilog testbench previously created, the output came out to be as follows: Figure 9: Top-level module simulation result of 8-bit accumulator. Comparing the outputs obtained in figure 9 with figures 7 and 1, it can be concluded that the circuit specified in the top-level module has the same behaviors as the 8--bit accumulator previously created in RTL and netlist models.

To verify the correctness of the logic synthesis and place and route steps, Equivalence checking using Formality was performed that use the 8-bit accumulator Verilog file “accu.v” as the reference and the top-level file “final.v” as the target for testing. The output of the process is as follows: Figure 10: Result of equivalent checking using Formality. As can be seen in the figure, the 8-bit accumulator specified in the Verilog file originally created and the 8-bit accumulator in the top-level module just generated was equivalent. As the top-level design was successfully generated, the next step would be to generate the layout in Virtuoso platform. The “OSU_stdcells” library was used to help generating the layout of the circuit. After finished generating the layout, the output came out to be as follows:

a) b) Figure 11: Layout of the 8-bit accumulator circui a) Symbol level view; b) Transistor level view.

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Thus the layout of the 8-bit accumulator was successfully generated using the Verilog file “accu.v” Deliverable questions 1) What is a standard cell? A standard cell is a logic gate with a layout designed for a specific fabrication process. For a particular fabrication process, standard cells for different kinds of logic gates or different sizes of a same logic gate are usually grouped into a standard cell library. 2) What are the differences among “accu.v”, “accu.vh”, and “final.v”? The “accu.v” file is the Verilog file of the 8-bit accumulator that only contains the general designs and implementation of the accumulator without any real parameters of the components The “accu.vh” file is the gate-level netlist that contains more information of the accumulator such as the interconnected standard cells of the circuit. The “final.v” file is the top-level netlist that contains the most information of the accumulator such as the interconnected standard cells’ locations and connections (where and how the cells are placed and routed). 3) How does the area of your design change after place&route? Observing the area specified in figures 4 and 8, it can be seen that the area has increased from 155.3 μ m 2 to 158.6 μ m 2 4) How does the timing of your design change after place & route?

Figure 12: A snippet of the new timing after place & route Comparing the result in figure 12 with figure 5, the time consumption of the circuit has significantly reduced. 5) Why do we need to use Virtuoso to generate the final layout for fabrication? What information is available from “final.gds2”? We need Virtuoso platform because this is the platform specifically designed to create layouts and schematics of circuits. The 'final.gds2' contains only the placement of the cells and the metal interconnects. It doesn't contain any layout details inside the cells, e.g. wells and poly. Therefore, we need to combine this stream with cell layouts to obtain the final layout for fabrication. Conclusions In this lab, an 8-bit accumulator layout was successfully created using the Verilog file “accu.v” that only contains the general designs and implementation of the accumulator without any real parameters of the components. Through the lab, standard cell-based ASIC design flow was introduced together with various tools and techniques necessary to generate the layout of a circuit from hardware description language. Everything was straightforward, and there was no major problem during the experiment process. Overall, everything implemented in this lab was functioning properly. Thanks to this lab, users would have the opportunity to learn about standard cell-based ASIC design flows as wells as practice all the new design techniques and testing tools such as OSU standard cell library, Synopsys Design Compiler, Synopsys Formality, Cadence Encounter Digital Implementation System, and Cadence Virtuoso.

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