ECE 429 lab 8 report

docx

School

Illinois Institute Of Technology *

*We aren’t endorsed by this school

Course

429

Subject

Electrical Engineering

Date

Feb 20, 2024

Type

docx

Pages

Uploaded by UltraFogKomodoDragon19

ECE 429 Laboratory Report #8 Carry-Ripple Addition III By Phu Trinh ECE 429-L01 Prof. Ken Choi TA: Victoria Kim Lab date: 11/02/2022 Due date: 11/09/2022

Introduction This lab is the last part if the series of three labs to implement a complete schematic and layout of a 4-bit carry-ripple adder. In this lab, both the schematic and the layout of the 4-bit full adder will be implemented using the hierarchical design that utilizes the layout and the schematic of the 1-bit full adder implemented in the previous two labs. The layout of the 4-bit full adder would be tested using DRC and LVS tools to ensure that the layout follows all the design rules and that the schematic and layout of the 4-bit full adder created will have the same functionalities. After that, a test circuit schematic will be implemented that uses the 4-bit full adder as the core component, and a SPICE netlist will be generated based on that circuit. Then, a Verilog file of the 4-bit full adder will be created, and a test Verilog program will also be implemented to make sure that the 4-bit adder Verilog program would function properly. Using ESP tool, the SPICE netlist of the 4-bit full adder circuit will be compared against the Verilog file to make sure that the schematic and layout created in this lab would have the desired behaviors. Finally, some key characteristics of the 4-bit full adder gate such as propagation rising and falling delays will also be measured. Theory and Pre-lab Theory The theory behind this lab is to practice implementing VLSI circuit layouts and schematics using hierarchical design, which allows the implementation of a circuit using schematic and layouts that were created in previous labs. The equivalent checking technique using ESP, will also be practiced to verify the logic functionality of the circuit designs. Preliminary questions 2) Translate the following two sets of inputs to binary  11 + 5 = b1011 + b0101  4 + 10 = b0100 + b1010 After reading through the lab manual and performing the preliminary works, the previous labs and tools previously utilized were carefully reviewed to prepare for the lab session. Implementation First, two Verilog files were created, one is a 4-bit full adder, while the other one is the test program to test the functionalities of 4-bit full adder. The two programs are displayed in the figures below.

Figure 1: Verilog 4-bit adder program Figure 2: Verilog test program for the 4-bit full adder Figure 1 is the program of the 4-bit full adder, in which the behavior of the adder is implemented. Figure 2 is the test program, which contains 6 different test cases for the 4-bit full adder. When running the Verilog files, the output obtained was as follows:

Your preview ends here

Eager to read complete document? Join bartleby learn and gain access to the full version

Access to all documents
Unlimited textbook solutions
24/7 expert homework help

Figure 3: Output when running the Verilog files. As can be seen in figure 3, all six test cases were displayed that show the correct results for all the sets of inputs. Therefore, the Verilog 4-bit adder were functioning properly that has the desired behaviors. The 4-bit carry ripple adder schematic was implemented using four different instances of the 1- bit full adder created in previous lab. For the first 1-bit full adder, the ci input is connected to the ground, whereas for the other three 1-bit full adders, the ci of the next stage is connected to the co of the previous stage. When the schematic was successfully implemented, a schematic symbol was generated using the built-in tool of Virtuoso. The 4-bit carry-ripple adder schematic and symbol are shown in the figure below. a) b) Figure 4: Schematic and schematic symbol of the 4-bit carry-ripple adder. a) Schematic; b) Schematic symbol.

Instead of being implemented using transistors, the 4-bit carry-ripple adder was implemented using the 1-bit full adder implemented in previous lab via the hierarchical design technique. Both the schematic and the schematic symbol of the AND gate were checked using “Check and Save” function, and there was no error found. The layout of the 4-bit carry ripple adder was also implemented using the hierarchical design technique that utilizes the design layout of the 1-bit full adder. For the first 1-bit adder, the ci input is connected to the ground, whereas the ci of all other 1-bit adders were connected to the co of the adder on its immediate left. The vdd! and gnd! bars of all the adder were connected together using ‘metal1’. Some of the input and output pins were redrawn to make them show up in the new layout. The layout of the 4-bit carry ripple adder is as shown a) b) Figure 5: Layout of 4-bit carry-ripple adder a) Symbol level view; b) Transistor level view. After the 4-bit carry-ripple adder was created, it was then tested to see if the design followed all the design rules specified by FreePDK45 using the built-in DRC tool. The result is as shown.

a) DRC control window b) Report summary window c) Calibre RVE window Figure 6: DRC checking result of 4-bit CRA layout a) DRC control window; b) Report summary window; c) Calibre RVE window As seen in figure 6 c), there was no error found, indicated by the line “No Result Found,” so the inverter layout was correctly created following all the design rules. However, there were some warnings as shown in figure 6 a) but those warnings are not relevant for this lab. Similar to before, to test whether the inverter layout just created would function as an AND gate, the built-in LVS tool was used that would take a schematic and a layout as the inputs to compare whether the two were constructed with the same set of transistors and interconnection. The AND

Your preview ends here

Eager to read complete document? Join bartleby learn and gain access to the full version

Access to all documents
Unlimited textbook solutions
24/7 expert homework help

layout will be tested against the AND schematic created in the previous lab. The output of the LVS test is shown in figure 10 below. a) b) c) Figure 7: LVS checking result of 4-bit CRA layout a) LVS control window; b) Report summary window; c) Calibre RVE window Again, as seen in both figure 7 b) and figure 7 c), the result was a smiley face, indicating that the layout was correctly created that would function like an inverter. There were some warnings again as seen in figure 7 a), but those warnings are not relevant to the lab. This has confirmed that the layout design of the 4-bit CRA has the same functionality as the 4-bit CRA schematic implemented before.

In this lab, the PEX built-in tool was also run to generate an fa4bit netlist file that would be used for simulation later. The output of the process is displayed in the figure below. a) b) Figure 8: PEX checking result and netlist file of 4-bit CRA layout a) PEX control window; b) PEX netlist file A test circuit that utilize the 4-bit CRA as the main building block was implemented. The design of that circuit is as follows. Figure 9: 4-bit CRA test circuit

After extracting the SPICE netlist from the circuit above, the netlist was then modified to take the 4-bit CRA netlist design and simulate that in order to obtain the propagation delays between a0-s3 and a0-co in the signal transition from A + B = 11 + 5 => 4 + 10. The spice netlist is as follows:

Your preview ends here

Eager to read complete document? Join bartleby learn and gain access to the full version

Access to all documents
Unlimited textbook solutions
24/7 expert homework help

Figure 10: Modified SPICE netlist for 4-bit CRA circuit. The functionalities of the 4-bit CRA design created using Virtuoso was tested against the previously implemented Verilog 4-bit full adder file using Formality ESP platform and see whether the 4-bit CRA would have the expected behavior. The output is as follows.

Figure 12: Equivalent checking result of Verilog and Schematic. As can be seen in the figure, the output came out to be “Passed,” indicating that the 4-bit CRA schematic created would behave the same way as the 4-bit CRA specified in the Verilog file. After successfully confirming the behavior of the 4-bit CRA, the next step would be to observe and analyze the propagation rising and falling delays using the SPICE netlist shown in figure 10. The output obtained when simulating the netlist file is as follows:

Figure 13: Propagation delays of 4-bit CRA, signal transition A + B = 11 + 5 => 4 + 10 (lab8.mt0) Observing figure 13, it can be seen that the rising propagation delay from a0 to s3 is smaller than the falling propagation delay from a0-s3. On the other hand, the rising propagation delay from a0 to co is larger than the falling propagation delay from a0-co. generally, the propagation delays from a0 to co is larger than those of from a0-s3. Deliverable questions 1) How is the functionality of your adder design validated/verified at various abstraction levels? In the Verilog file, the 4-bit CRA was tested using a test program that contain different test cases. By executing the Verilog files and observing that the outputs of all the test cases were as desired, it was concluded that the Verilog 4-bit CRA was functioning as expected. The transistor schematic and layout designs of the 4-bit CRA was compared against each other to make sure that they have the same functionalities before comparing the 4-bit CRA schematic to

Your preview ends here

Eager to read complete document? Join bartleby learn and gain access to the full version

Access to all documents
Unlimited textbook solutions
24/7 expert homework help

the previously tested Verilog 4-bit CRA. Since they all showed the same behaviors as the tested Verilog 4-bit CRA, the adder schematic and layout designs were validated. Conclusions The 4-bit CRA schematic and layout were successfully created and tested using hierarchical techniques that utilize the schematic and layout of the 1-bit mirror adder previously implemented in the previous lab. Overall, the 4-bit CRA designed showed the desired characteristics identical to that of a Verilog 4-bit full adder. Everything was straightforward, and there was no major problem during the experiment process. Overall, everything implemented in this lab was functioning properly. Thanks to this lab, users would have the opportunity to practice all the design techniques and testing tools introduced in the previous lab as well as effectively utilize the designs implemented before.