230_HW5

Homework 5 ECE 230 Fall 2023 100110101101110101011101110001000001010101011101011000100101000010100010011100100001100101110001000001010101011101011000100101000110111010101110111001001011 Submit your solutions on D2L by Thursday Oct. 12, 8pm Instructions Please review the “How to Complete Weekly Homework” guide posted on D2L-Getting Started and the additional instructions from Homework 0 for submitting your work within this Word file. Problems: Part A -Strengthen your memory To help remember what we learned way back a week ago, complete these quick memory refreshers. 1. Answer the following Chapter 4 practice problems. a. Simplify the following logic equations by constructing the appropriate K-map, circling terms that can be combined, and writing the simplified equation. i. y = a’b + ab’ + ab ii. y = a’b’c’ + a’b’c + a’bc + abc’ + abc b. Apply DeMorgan’s laws to the following expressions to create an equivalent expression i. (a’b)’ = ?? ii. a+b’ = ?? iii. (a + b + c’)’ = ?? Click or tap here to enter text. Problems: Part B -XOR/XNOR and NAND/NOR 2. Answer the following questions about XOR/XNOR a. What does the X stand for in XOR/XNOR? b. Which 2- input gate will output high (1) if both inputs are 1’s? c. Which 2-input gate will output high if the inputs are different from each other? d. What is a XNOR b in sum-of-minterms form? e. What is the C and Verilog operator notation for XOR? f. What is 0 ^ 1 = ? g. What is ~(0 ^ 0) = ? h. What multi- input logic gate will output a 1 if the number of inputs that are 1’s is odd? Click or tap here to enter text. 3. What is the even parity bit (1 or 0) for the following 7-bit transmissions? Explain why. a. 1101111 b. 0011001 Click or tap here to enter text. 4. Answer the following questions about NAND/NOR a. Which 2-input logic gate is high only when both inputs are low? b. Which 2-input logic gate is low only when both inputs are high? c. How do NAND and NOR gate symbols differ from AND and OR symbols? d. Which logic gate(s) are universal gates, able to implement all combinational logic functions with a single type of gate?

e. Describe two reasons we might use NAND and NOR gates (rather than using AND and OR gates)? Hint: see question (d) for one reason. f. Sketch a schematic showing how each of the following logic functions can be formed only using NOR gates. Hints: This was done for NAND in the course notes and textbook. OR should be easy, but AND will require using DeMorgan’s. i. NOT ii. AND iii. OR Click or tap here to enter text. 5. Use the bubble pushing technique to show how the circuit below can be converted to a NAND- only universal gate circuit. Draw a series of circuits that highlight the steps in this conversion, and briefly describe what is happening in each conversion step. Click or tap here to enter text. Problems: Part C -MUXs 6. Answer the following questions about MUXs. a. How many outputs does a 2:1 MUX have? How about a 4:1 MUX? b. For a 2:1 MUX with inputs i0,i1, what is output y if select, s, = 1? c. For a 2:1 MUX with inputs i0,i1, what value of select, s, will set output y = i1? d. For a 4:1 MUX with inputs i0,i1,i2,i3, what value of select, s 1 s 0 , will set output y = i0? e. For a 4:1 MUX with inputs i0,i1,i2,i3, what value of select, s 1 s 0 , will set output y = i2? f. For a 4:1 MUX with inputs i0,i1,i2,i3, what is output y if selects, s 1 s 0 , = 01? g. How many select lines would be needed for a 32:1 MUX? h. If we needed to implement a MUX to select one output from 7 inputs, what size MUX and how many select lines would be needed? Click or tap here to enter text. 7. Sketch a schematic that would implement a 16:1 MUX for the conditions below. For all sketches, correctly show which select signal should be connected. a. How many select signals would be needed for a 16:1 MUX? b. Sketch a 16:1 MUX composed of 8:1 and 2:1 MUXs. Hints: this will look similar to the 8:1 MUX shown in course notes. c. Sketch a 16:1 MUX composed entirely of 4:1 MUXs. Click or tap here to enter text. 8. Imagine you are designing an interface to a memory that stores 64-bit passwords for 128 different users. You decide you need a N-bit K:1 MUX to output all 64- bits of a user’s password every time you input 1 of 32 user IDs. What is K, what is M and how many select lines are needed for this MUX? Explain your choices. Click or tap here to enter text. because they're universal gates (not) y = AB (and) a I = I a I = y = ay = x + b(0m) b I 2 outputs /4 outputs y = it S = 1 00 10 y = i1 25 = 32 , so 5 3 : 1 MUx with 2 select lines 24 = 16 So 4 ⑧ F = 128 users (128 different users) N = T (log2(128) = 7) S . L . =7 lines (2 = 128)